Option Gated Replay
Example program
(c) Spectrum GmbH
63
Number of samples on gate signal
As described above there’s a delay at the start of the gate interval due to the internal memory structure. However this delay can be partly
compensated by internal pipelines resulting in a data delay that even can be negative showing the trigger event (acquisition mode only). This
data delay is listed in an extra table. But beneath this compensation there’s still the start delay that as a result causes the card to use less
samples than the gate signal length. Please refer to the following table to see how many samples less than the length of gate signal are used.
Allowed trigger modes
As mentioned above not all of the possible trigger modes can be used as a gate condition. The following table is showing the allowed trig-
ger modes that can be used and explains the event that has to be detected for gate-start end for gate-end.
External TTL edge trigger
Example program
The following example shows how to set up the board for Gated Replay in standard mode. The setup would be similar in FIFO mode, but the
memsize register would not be used.
Module 0
Module 1
0
1
0
1
Mode
Sampling clock
less samples
Sampling clock less samples
X
Standard/FIFO
< 10 MS/s
14
> 10 MS/s
24
X
X
Standard
< 10 MS/s
14
> 10MS/s
24
X
X
FIFO
< 5 MS/s
6
> 5 MS/s
12
X
X
Standard/FIFO
< 5 MS/s
6
> 5 MS/s
12
X
X
X
X
Standard
< 5 MS/s
6
> 5 MS/s
12
X
X
X
X
FIFO
< 2.5 MS/s
4
> 2.5 MS/s
6
Mode
Gate start will be detected on
Gate end will be detected on
TM_TTLPOS
positive edge on external trigger
negative edge on external trigger
TM_TTL_NEG
negative edge on external trigger
positive edge on external trigger
SpcSetParam (hDrv, SPC_GATE, 1); // Enables Gated Replay
SpcSetParam (hDrv, SPC_MEMSIZE, 4096); // Set the total memsize of generation to 4096 samples
SpcSetParam (hDrv, SPC_TRIGGERMODE, TM_TTLPOS); // Sets the gate condition to external TTL mode, so that
// data is replayed, if the signal is at HIGH level
