Introduction
Hardware information
(c) Spectrum GmbH
11
Hardware information
Block diagram
Technical Data
Resolution
8 Bit
Dimension
312 mm x 107 mm
Integral linearity (DAC)
± 1.5 LSB typ.
Width (Standard)
1 full size slot
Differential linearity (DAC)
± 1.0 LSB typ.
Width (with star hub option)
2 full size slots
Output resistance
< 1 Ohm
Width Amplifier option
1 half size slot
Max output swing in 50 Ohm
± 3 V ( amplitude)
Analogue connector
3 mm SMB male
Max slew rate (no filter)
> 0.9 V/ns
Warm up time
10 minutes
Multi: Trigger to 1st sample delay
fixed
Operating temperature
0°C - 50°C
Multi: Recovery time
< 20 samples
Storage temperature
-10°C - 70°C
Ext. clock: delay to internal clock
42 ns ± 2 ns
Humidity
10% to 90%
Output to trigger out delay 1 channel
<10 MS/s: -10 sampl., >10 MS/s: -42 sampl. Offset stepsize
< 2 mV
Output to trigger out delay 2 channels
<5 MS/s: -5 sampl., > 5 MS/s: -21 sampl.
Amplitude stepsize
< 1 mV
Crosstalk @ 1 MHz signal ±3 V
< -80 dB
Output accuracy
< 1%
Min internal clock
1 kS/s
Power consumption 5 V @ full speed
max 3.7 A (18.5 Watt)
Min external clock
DC
Power consumption 5 V @ power down
max 2.3 A (11.5 Watt)
Trigger input:Standard TTL level
Low: -0.5 > level < 0.8 V
High: 2.0 V > level < 5.5 V
Trigger pulse must be valid > 2 clock periods.
Clock input: Standard TTL level
Low: -0.5 V > level < 0.8 V
High: 2.0 V > level < 5.5 V
Rising edge. Duty cycle: 50% ± 5%
Trigger output
Standard TTL, capable of driving 50 Ohm.
Low < 0.4 V (@ 20 mA, max 64 mA)
High > 2.4 V (@ -20 mA, max -48 mA)
One positive edge after the first internal trigger
Clock output
Standard TTL, capable of driving 50 Ohm
Low < 0.4 V (@ 20 mA, max 64 mA)
High > 2.4 V (@ -20 mA, max -48 mA)
