Sony WLL-RX55, Maintenance Manual

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1-10 (E)
WLL-RX55
1-6-3. DEC-146 Board
The DEC-146 board decodes the TS signal (a stream of
MPEG2) transferred from the RX-89 board, and then
outputs baseband video/audio signals.
The MPEG2 decoder module and the PLD IC make up the
majority of the whole circuit.
A REF SYNC circuit, an SDRAM, an audio rate converter,
and a character generator are provided around the PLD IC.
MPEG2 Decoder
The MPEG2 decoder decodes the TS signal transferred
from the RX-89 board to a baseband signal to generate
baseband data and 27 MHz clock. Since the output signal
is decoded from the ASI signal, the output signal contains
many PCR jitters specific to DVB.
DVB: Digital Video Broadcasting
PCR: Program Clock Reference
REF SYNC Circuit
This circuit generates a 27 MHz signal locked to the REF
signal transferred from the REFERENCE terminal on the
DI-44 board on the rear panel. It also performs detection of
REFERENCE signal input and simple sampling of color
burst.
Frame Synchronizer
The frame synchronizer is composed of an internal circuit
of the PLD IC and SDRAM IC402.
The synchronizer can suppress large amount of jitters
contained in the baseband video data from the MPEG2
decoder module to an amount level that meets the broad-
casting quality. It also performs synchronization in case
WLL-CA55 is not synchronized with the CCU side.
Audio Rate Converter
Main functions of the audio rate converter IC400 are, like
the frame synchronizer, to change the clock of CCU and to
absorb jitters.
PLD
The PLD IC100 incorporates a frame synchronizer, a
video/audio test signal generator, a character superimpos-
ing circuit, an SDI encoder, and a control circuit for each
block of this board.
Characters can be superimposed on the SDI signal and the
main-line video signal.
The SDI encoder outputs the decoded baseband signal
from the unit. Three SDI signals are output from the unit
via the cable driver on the DR-524 board.
1-6-4. DI-44 Board
The DI-44 board is composed of an ASI input (STREAM-
1, 2) circuit for the diversity configuration and a REFER-
ENCE input buffer.
The ASI input signals are received by the equalizer and the
PECL/LVPECL conversion buffer, and then output to the
RX-89 board.
The REFERENCE signal is output to the DEC-146 board
through the 6 dB amplifier. This board contains a loop-
through terminal for the REFERENCE input signal.
1-6-5. DR-524 Board
The DR-524 board is a buffer board to output three SDI
signals from the DEC-146 board to the external unit. The
SDI signal of LVPECL differential signal form, which is
transferred from the DEC-146 board, is converted to PECL
and then output by the 5 V driver.
The analog video signal from the VA-220 board is output
from the CN-2492 board on the rear panel through the DR-
524 board to the external unit.
1-6-6. VA-220 Board
The VA-220 board generates analog video signals for
external output from 4:2:2 digital signals transferred from
the DEC-146 board.
The 4:2:2 parallel digital signals are latched by the FPGA
IC31 and then D/A converted by IC101.
This board generates the analog luminance signal from
IC101, chroma signal, analog video signals (for external
output) from RGB signals, WF signal, PIX signal, RCP
video signal, and FRONT PANEL signal.
Serial character data sent from the AT-156 board is
converted to an analog signal by IC801, and then merged
with the PIX signal and FRONT PANEL signal. The
character data from the front panel is also merged with the
FRONT PANEL signal. IC805 and IC806 select the
character data transferred from the AT-156 board or front
panel.
The waveform monitor control signals generated in the
FPGA IC31 are output from the WF MODE connector
through the CN-2493 board to the external unit.