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C-128
SRX-R320
C-128
2
3
4
5
1
A B C D E F G H
PR-300 (4/25)
SUFFIX: -15
PR-300 (4/25)
SUFFIX: -15
PR-300 (4/25)
BOARD NO. 1-873-515-15
0
VS1
VS2
3.3V
0
1.25V
VID voltage select settings
1.2V
0
User Selectable
0
1
1.5V
1
1
1
1
Vout
0
0
1
0
0.8V
0
VS0
VID
2.5V
1
0
1
1.8V
0
1
0
0
1
1
1
DFD data output 77MHz
Open drain
DFD clock 77MHz
DFD clock 77MHz
30ohm@100MHz
Max 1500mA
1608
Open drain
Open drain
1608
CDCVF25081 Function table
1 1 Atv Atv PLL
1 0 Atv Atv Bypass
0 1 Atv HiZ PLL
0 0 HiZ HiZ N/A
S2 S1 1Y 2Y OUTPUT
L:DOWN
H: UP
Rx FPGA mode
Spec
50ohm +/-1%
On Chip Termination
or
25ohm +/-1%
Calibration Resistor
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
DFD clock 77MHz
DFD data output 77MHz
DFD data output 77MHz
DFD data output 77MHz
DFD data output 77MHz
Clock input 77MHz
On Chip Termination
or
25ohm +/-1%
Calibration Resistor
Spec
50ohm +/-1%
LVTTL / VCCIO=3.0V
LVTTL / VCCIO=3.0V
LVTTL / VCCIO=3.0V
LVTTL / VCCIO=3.0V
LVTTL / VCCIO=3.0V
LVDS / VCCIO=2.5V
LVDS / VCCIO=2.5V
LVTTL / VCCIO=3.0V
in the chain
1st device
Diff 100ohm
308MHz (77Mx4)
LVDS IN
100hm (0.5%)
LVDS termination
Diff 100ohm
308MHz (77Mx4)
LVDS IN
100hm (0.5%)
LVDS termination
pull-down resistors that are always active.
The MSEL[3..0] pins have 9kohm internal
0
PS Standard POR(3.3/3.0/2.5V)
0
0 0
0
0
0
Configuration schemes
0
AS Fast POR(3.3V)
1
1
Cyclone III Configuration schemes
0
1
0
AS Standard POR(3.0/2.5V)
1
1
AS Standard POR(3.3V)
1 0
AS Fast POR(3.0/2.5V)
1 0
(3) 2
1 0
MSEL
0
30ohm@100MHz
Max 1500mA
Max 200mA
1000ohm@100MHz
1005
Open drain
Open drain
Open drain
Open drain
*EGRN[2]
*ERED[1]
*EGRN[9]
*ERED[9]
*ERED[0]
*OGRN[6]
*EGRN[7]
*EBLU[0]
*ERED[4]
*OGRN[5]
*ERED[7]
*EBLU[7]
*ERED[8]
*EGRN[6]
*OGRN[8]
*EGRN[1]
*EGRN[8]
*EBLU[3]
*EBLU[2]
*EBLU[6]
*ERED[3]
*ERED[6]
*EBLU[8]
*EBLU[9]
*EGRN[4]
*ERED[2]
*EBLU[1]
*EBLU[4]
*OGRN[7]
*EGRN[3]
*ERED[5]
*OGRN[9]
*OGRN[4]
*OGRN[0]
*OGRN[3]
*EGRN[0]
*EBLU[5]
*OGRN[2]
*EGRN[5]
*OGRN[1]
*ORED[0]
*OBLU[3]
*ORED[3]
*OBLU[7]
*OBLU[2]
*ORED[7]
*ORED[9]
*OBLU[0]
*OBLU[8]
*OBLU[9]
*OBLU[1]
*OBLU[6]
*OBLU[5]
*OBLU[4]
*ORED[8]
*ORED[5]
*ORED[6]
*ORED[1]
*ORED[2]
*ORED[4]
E12
GNDA2
F12
VCCA2
M5
GNDA1
L5
VCCA1
R15
GND:28
R2
GND:27
P12
GND:26
P5
GND:25
N10
GND:24
N7
GND:23
M13
GND:22
M4
GND:21
K13
GND:20
K4
GND:19
J10
GND:18
J9
GND:17
J8
GND:16
J7
GND:15
H10
GND:14
H9
GND:13
H8
GND:12
H7
GND:11
G13
GND:10
G4
GND:9
E13
GND:8
E4
GND:7
D10
GND:6
D7
GND:5
C12
GND:4
C5
GND:3
B15
GND:2
B2
GND:1
D13
VCCD_PLL2
N4
VCCD_PLL1
K7
VCCINT:8
H11
VCCINT:7
H6
VCCINT:6
G10
VCCINT:5
G9
VCCINT:4
G8
VCCINT:3
G7
VCCINT:2
G6
VCCINT:1
C7
VCCIO8:3
C4
VCCIO8:2
A1
VCCIO8:1
C13
VCCIO7:3
C10
VCCIO7:2
A16
VCCIO7:1
G14
VCCIO6:2
E14
VCCIO6:1
M14
VCCIO5:2
K14
VCCIO5:1
T16
VCCIO4:3
P13
VCCIO4:2
P10
VCCIO4:1
T1
VCCIO3:3
P7
VCCIO3:2
P4
VCCIO3:1
M3
VCCIO2:2
K3
VCCIO2:1
G3
VCCIO1:2
E3
VCCIO1:1
IC400
(9/9)
EP3C5F256C8N(60)
E6
IO/DATA6
E7
IO/DATA5
D8
IO:5
C8
IO:3
C6
IO/VREFB8N0
B8
IO/DIFFIO_T11p
A8
IO/DIFFIO_T11n
F8
IO/DIFFIO_T10p/DATA3
E8
IO/DIFFIO_T10n/DATA2
B7
IO/DIFFIO_T9p/DATA4
A7
IO/DIFFIO_T9n
F7
IO/DIFFIO_T8p
F6
IO/DIFFIO_T8n
B6
IO/DIFFIO_T7p
A6
IO/DIFFIO_T7n
A5
IO/DIFFIO_T6n/DATA7
B5
IO/DIFFIO_T5p
A2
IO/DIFFIO_T5n
B4
IO/DIFFIO_T4p
A4
IO/DIFFIO_T4n
D6
IO/DIFFIO_T3p
D5
IO/DIFFIO_T3n
B3
IO/DIFFIO_T2p
A3
IO/DIFFIO_T2n
D3
IO/DIFFIO_T1p
C3
IO/DIFFIO_T1n
IC400
(8/9)
EP3C5F256C8N(60)
IOBANK_8
E9
IO:7
C11
IO/VREFB7N0
E11
IO/RUP4
E10
IO/RDN4
D14
IO/DIFFIO_T21p
C14
IO/DIFFIO_T21n
D12
IO/DIFFIO_T20p
D11
IO/DIFFIO_T20n
B13
IO/DIFFIO_T19p
A13
IO/DIFFIO_T19n
B12
IO/DIFFIO_T18p
A12
IO/DIFFIO_T18n
B11
IO/DIFFIO_T17p
A11
IO/DIFFIO_T17n
F9
IO/DIFFIO_T16p
F10
IO/DIFFIO_T16n
A15
IO/DIFFIO_T15p
F11
IO/DIFFIO_T15n
B10
IO/DIFFIO_T14p
A10
IO/DIFFIO_T14n
D9
IO/DIFFIO_T13p
C9
IO/DIFFIO_T13n
B9
IO/DIFFIO_T12p
A9
IO/DIFFIO_T12n
B14
IO/PLL2_CLKOUTp
A14
IO/PLL2_CLKOUTn
IC400
(7/9)
EP3C5F256C8N(60)
IOBANK_7
G12
MSEL2
H12
MSEL1
H13
MSEL0
H14
CONF_DONE
G11
IO:11
F13
IO:9
B16
IO:2
F14
IO/VREFB6N0
H15
IO/DIFFIO_R5p
H16
IO/DIFFIO_R5n
G15
IO/DIFFIO_R4p/CRC_ERROR
G16
IO/DIFFIO_R4n/INIT_DONE
F15
IO/DIFFIO_R3p/CLKUSR
F16
IO/DIFFIO_R3n/nCEO
D15
IO/DIFFIO_R2p
D16
IO/DIFFIO_R2n
C15
IO/DIFFIO_R1p
C16
IO/DIFFIO_R1n
E16
CLK5/DIFFCLK_2n
E15
CLK4/DIFFCLK_2p
IC400
(6/9)
EP3C5F256C8N(60)
IOBANK_6
N13
IO:22
M12
IO:21
L13
IO:19
L12
IO:18
K12
IO:16
K11
IO:15
J13
IO:14
J11
IO:13
L14
IO/VREFB5N0
N14
IO/RUP3
P15
IO/RDN3
R16
IO/DIFFIO_R11p
P16
IO/DIFFIO_R11n
N15
IO/DIFFIO_R10p
N16
IO/DIFFIO_R10n
L15
IO/DIFFIO_R9p
L16
IO/DIFFIO_R9n
K15
IO/DIFFIO_R8p
K16
IO/DIFFIO_R8n
J15
IO/DIFFIO_R7p/DEV_CLRn
J16
IO/DIFFIO_R7n/DEV_OE
J12
IO/DIFFIO_R6p
J14
IO/DIFFIO_R6n
M16
CLK7/DIFFCLK_3n
M15
CLK6/DIFFCLK_3p
IC400
(5/9)
EP3C5F256C8N(60)
IOBANK_5
R14
IO:25
P9
IO:23
P11
IO/VREFB4N0
M10
IO/RUP2
N11
IO/RDN2
M11
IO/DIFFIO_B22p
N12
IO/DIFFIO_B22n
P14
IO/DIFFIO_B21p
L11
IO/DIFFIO_B21n
T14
IO/DIFFIO_B20p
T15
IO/DIFFIO_B20n
R13
IO/DIFFIO_B19p
T13
IO/DIFFIO_B19n
K10
IO/DIFFIO_B18p
L10
IO/DIFFIO_B18n
R12
IO/DIFFIO_B17p
T12
IO/DIFFIO_B17n
R11
IO/DIFFIO_B16p
T11
IO/DIFFIO_B16n
R10
IO/DIFFIO_B15p
T10
IO/DIFFIO_B15n
M9
IO/DIFFIO_B14p
N9
IO/DIFFIO_B14n
K9
IO/DIFFIO_B13p
L9
IO/DIFFIO_B13n
R9
IO/DIFFIO_B12p
T9
IO/DIFFIO_B12n
IC400
(4/9)
EP3C5F256C8N(60)
IOBANK_4
T2
IO:26
M6
IO:20
L7
IO:17
P6
IO/VREFB3N0
R8
IO/DIFFIO_B11p
T8
IO/DIFFIO_B11n
N8
IO/DIFFIO_B10p
P8
IO/DIFFIO_B10n
L8
IO/DIFFIO_B9p
M8
IO/DIFFIO_B9n
R7
IO/DIFFIO_B8p
T7
IO/DIFFIO_B8n
R6
IO/DIFFIO_B7p
T6
IO/DIFFIO_B7n
R5
IO/DIFFIO_B6p
T5
IO/DIFFIO_B6n
M7
IO/DIFFIO_B5p
K8
IO/DIFFIO_B5n
N5
IO/DIFFIO_B4p
N6
IO/DIFFIO_B4n
R3
IO/DIFFIO_B2p
T3
IO/DIFFIO_B2n
N3
IO/DIFFIO_B1p
P3
IO/DIFFIO_B1n
R4
IO/PLL1_CLKOUTp
T4
IO/PLL1_CLKOUTn
IC400
(3/9)
EP3C5F256C8N(60)
IOBANK_3
R1
IO:24
J6
IO:12
L3
IO/VREFB2N0
K5
IO/RUP1
L4
IO/RDN1
P2
IO/DIFFIO_L10p
P1
IO/DIFFIO_L10n
N2
IO/DIFFIO_L9p
N1
IO/DIFFIO_L9n
L2
IO/DIFFIO_L8p
L1
IO/DIFFIO_L8n
K2
IO/DIFFIO_L7p
K1
IO/DIFFIO_L7n
K6
IO/DIFFIO_L6p
L6
IO/DIFFIO_L6n
J2
IO/DIFFIO_L5p
J1
IO/DIFFIO_L5n
M1
CLK3/DIFFCLK_1n
M2
CLK2/DIFFCLK_1p
IC400
(2/9)
EP3C5F256C8N(60)
IOBANK_2
H1
DCLK
H2
IO/DATA0
F4
nSTATUS
H5
nCONFIG
J3
nCE
J5
TMS
J4
TDO
H4
TDI
H3
TCK
G5
IO:10
F5
IO:8
E5
IO:6
D4
IO:4
B1
IO:1
F3
IO/VREFB1N0
G2
IO/DIFFIO_L4p
G1
IO/DIFFIO_L4n
F2
IO/DIFFIO_L3p
F1
IO/DIFFIO_L3n
D2
IO/DIFFIO_L2p/FLASH_nCE/nCSO
D1
IO/DIFFIO_L2n
C2
IO/DIFFIO_L1p
C1
IO/DIFFIO_L1n/DATA1/ASDO
E1
CLK1/DIFFCLK_0n
E2
CLK0/DIFFCLK_0p
IC400
(1/9)
EP3C5F256C8N(60)
IOBANK_1
001-K8,004-B2,005-B1
SCL2_FPGA
001-K8,004-B2,005-B2
SDA2_FPGA
+3.0V_RXU
D402
1SS388
C443
4.7uF
R445
22
001-B4,003-D8,003-F3,003-L6,014-G9,017-L7,018-F9,021-L7,022-F9,025-L7
PR_PWR_ERR
+3.0V
C440
0.1uF
16V
25
EPAD
24
NC[SW]:5
23
NC[SW]:4
22
NC[SW]:3
21
NC[SW]:2
20
PVIN:2
19
PVIN:1
18
ENABLE
17
POK
16
AVIN
15
AGND
14
VFB
13
VSENSE
12
VS0
11
VS1
10
VS2
9
PGND:4
8
PGND:3
7
VOUT:4
6
VOUT:3
5
VOUT:2
4
VOUT:1
3
PGND:2
2
PGND:1
1
NC[SW]:1
IC402
EN5322QI
C438
1uF
16V
1608
C439
0.1uF
16V
C442
22uF
6.3V
3216
+1.2V_RX
GND
C441
22uF
6.3V
3216
GND
+3.0V
C437
0.1uF
GND
C436
10uF
10V
3216
GND
004-E7,006-B1
DFD_IN_UP_EV_BLU
004-F5,008-C1
DFD_IN_UP_OD_BLU
+3.0V_RXU
+3.0V_RXU
+3.0V_RXU
+3.0V_RXU
+3.0V_RXU
GND
+3.0V_RXU
+3.0V_RXU
C403
10uF
FB400
+3.0V
FB401
C402 4.7uF
C428 1000pF
C427 1000pF
C404
0.1uF
C405
0.1uF
C406
0.1uF
C407
0.1uF
C408
0.1uF
C409
0.1uF
C410
0.1uF
C411
0.1uF
C412
0.1uF
C413
0.1uF
C414
0.1uF
C415
0.1uF
C416
0.1uF
C417
0.1uF
C418
0.1uF
C419
0.1uF
C420
0.1uF
C421
0.1uF
C422
0.1uF
C423
0.1uF
C430
0.1uF
C429
0.1uF
C424
0.1uF
C425
0.1uF
R407
22
R406
22
R405
22
R404
22
+3.3V
GND
11
2Y3
7
2Y1
15
1Y3
3
1Y1
6
2Y0
10
2Y2
4
VDD1
13
VDD2
14
1Y2
2
1Y0
8
S2
9
S1
12
GND2
5
GND1
16
FBIN
1
CLKIN
IC401
CDCVF25081PWR
022-B3
RESERVE_RXU_TXB_2
022-B3
RESERVE_RXU_TXB_1
018-B3
RESERVE_RXU_TXG_2
018-B3
RESERVE_RXU_TXG_1
004-K10
FPGA_MODE_RX_U
006-C8
CLKQDI_UP_EV_U
006-I8
CLKQDI_UP_EV_D
008-I8
CLKQDI_UP_OD_D
008-C8
CLKQDI_UP_OD_U
C400
0.1uF
+3.3V
GND
R440
22
R439
22
R438
22
004-I8
DFDCLK_UP_77M
004-B7
DFDCLK_UP_77M
R437
22
R432
10k
R433
0
R418
100
001-B2
004-I10
LED2_RX_U
GND
009-F6
SCL2_DFD
005-B5
RESERVE_RXU_RXD_1
001-L2
TD_SY_to_RX_U
R400
100
002-E8
RX_UP_DFD_RST_OU
004-I9
LED1_RX_U
007-F6
SDA1_DFD
R409
100
001-C2
QDI_U3-
001-B2
QDI_U12-
007-F6
SCL1_DFD
D401
SML-D12M8WT86SM
002-E2
CLK_77M_RX_U
R429
100
001-B2
Q
CL403
R414
100
006-C8
HDQDI_UP1
001-D2
008-C1
DFD_IN_UP_OD_RED
R425
100
001-B2
R402
100
001-B2
QDI_UCLK-
001-B2
QDI_U8-
002-E8
RX_UP_DFD_RST_EL
CL402
014-C9,018-B9,022-C9
RX_nCEO
001-C2
QDI_U13-
R415
100
001-B2
001-C2
QDI_U7-
GND
001-B2
QDI_U2-
R442
1k
002-I2
ASDO_RX_U
002-F6,005-F6,014-J2,018-J3,022-J2
RESET
001-D2
001-B2
001-D2
002-I3
nCSO_RX_U
CL401
008-C1
DFD_IN_UP_OD_GRN
002-E8
RX_UP_DFD_RST_OL
GND
006-C8
VDQDI_UP1
R411
100
R431
100
001-C2
QDI_U9-
R428
100
R401
100
001-B2
QDI_U10-
002-M3
DATA0_RX_U
R441
1k
R419
100
CL400
002-E7
RX_UP_DFD_RST_EU
001-D2
002-I2
DCLK_RX_U
R430
100
R426
100
R410
100
004-B6
FPGA_MODE_RX_U
005-B5
RESERVE_RXU_RXD_2
001-B2
R422
100
002-M6,005-B3,014-C9,018-B9,022-C9
nCONFIG
014-B3
RESERVE_RXU_TXR_1
004-B6,008-C1
DFD_IN_UP_OD_BLU
001-C2
QDI_U1-
001-B2
002-K8,005-B3,014-C9,018-B9,022-C9
nSTATUS
014-B3
RESERVE_RXU_TXR_2
R423
100
001-K7,014-J3,018-J3,022-J3
SDA1_FPGA
001-B2
QDI_U0-
R403
100
006-B1
DFD_IN_UP_EV_RED
001-C2
QDI_U11-
R443
1k
002-C7,005-J6,014-J7,018-J7,022-J7
INIT_DONE
+3.0V
001-D2
001-K8,004-B2,005-B2
SDA2_FPGA
001-B2
QDI_U4-
001-B2
001-C2
QDI_U15-
R413
100
002-K8,005-J6,014-C9,018-B9,022-C9
CONF_DONE
004-B8,006-B1
DFD_IN_UP_EV_BLU
001-K8,004-B1,005-B1
SCL2_FPGA
001-D2
001-B2
QDI_U14-
001-C2
QDI_U5-
001-D2
001-K7,014-J3,018-J3,022-J3
SCL1_FPGA
001-L1
TD_RX_U_to_SY
R412
100
006-B1
DFD_IN_UP_EV_GRN
008-C8
HDQDI_UP2
001-D2
001-L2
TCK_RX_U
R424
100
004-F5
LED1_RX_U
008-C8
VDQDI_UP2
D400
SML-D12M8WT86SM
R416
100
001-B2
001-L2
TMS_RX_U
004-F6
LED2_RX_U
009-F6
SDA2_DFD
R417
100
001-B2
QDI_U6-
R427
100
+2.5V
C431
0.1uF
C433
0.01uF
FB403
C401
22uF
GND
GND
GND
GND
GND
+1.2V_RX
C435
4.7uF
+2.5V_PLL
C434
0.01uF
C432
0.1uF
C426
0.1uF
FB402
Summary of Contents for SRX-R320
Page 1: ...DIGITAL CINEMA PROJECTOR SRX R320 SRX R320S SERVICE MANUAL 1st Edition Revised 2 ...
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Page 377: ...C 177 SRX R320 C 177 CT 259 CT 259 CT 259 B SIDE SUFFIX 11 CT 259 A SIDE SUFFIX 11 ...
Page 379: ...C 179 SRX R320 C 179 CT 259 CT 259 CT 259 B SIDE SUFFIX 22 CT 259 A SIDE SUFFIX 22 ...
Page 382: ...C 182 SRX R320 C 182 LPD 2 A SIDE SUFFIX 12 LPD 2 LPD 2 ...
Page 383: ...C 183 SRX R320 C 183 LPD 2 B SIDE SUFFIX 12 LPD 2 LPD 2 ...
Page 386: ...C 186 SRX R320 C 186 LPD 2 A SIDE SUFFIX 31 LPD 2 LPD 2 ...
Page 387: ...C 187 SRX R320 C 187 LPD 2 B SIDE SUFFIX 31 LPD 2 LPD 2 ...
Page 390: ...C 190 SRX R320 C 190 MX 113 A SIDE SUFFIX 11 MX 113 MX 113 ...
Page 391: ...C 191 SRX R320 C 191 MX 113 B SIDE SUFFIX 11 MX 113 MX 113 ...
Page 394: ...C 194 SRX R320 C 194 PR 300 A SIDE SUFFIX 11 PR 300 PR 300 ...
Page 395: ...C 195 SRX R320 C 195 PR 300 B SIDE SUFFIX 11 PR 300 PR 300 ...
Page 398: ...C 198 SRX R320 C 198 PR 300 A SIDE SUFFIX 15 PR 300 PR 300 ...
Page 399: ...C 199 SRX R320 C 199 PR 300 B SIDE SUFFIX 15 PR 300 PR 300 ...
Page 402: ...C 202 SRX R320 C 202 SY 378 A SIDE SUFFIX 11 SY 378 SY 378 ...
Page 403: ...C 203 SRX R320 C 203 SY 378 B SIDE SUFFIX 11 SY 378 SY 378 ...
Page 406: ...Sony Corporation SRX R320 SY SRX R320S SY J E 9 968 660 03 1 Printed in Japan 2012 6 32 2009 ...