37
PRS-500
Pin No.
Pin Name
I/O
Description
N15
TRST
I/O
Read/write from main CPU (Not used (Open))
P1
D14
I/O
32 bits data bus
P2
A5
O
25 bits address bus
P3
A4
O
25 bits address bus
P4
A3
O
25 bits address bus
P5
A2
O
25 bits address bus
P6
A1
O
25 bits address bus
P7
D6
I/O
32 bits data bus
P8
D5
I/O
32 bits data bus
P9
MA10
O
Address output for SDRAM
P10
MA11
O
Address output for SDRAM
P11
DQM1
O
Data enable output for SDRAM
P12
RAS
O
Raw address select output for SDRAM
P13
SDCKE1
O
Not used (Open)
P14
CLKO
O
Not used (Open)
P15
RESET_SF
—
Not used (Open)
R1
A6
O
25 bits address bus
R2
D11
I/O
32 bits data bus
R3
EB1
O
Not used (Open)
R4
EB2
O
Byte strobe (D15
-
8)
R5
OE
O
Output enable
R6
D7
I/O
32 bits data bus
R7
A0
O
25 bits address bus
R8
SDCLK
O
Clock output for SDRAM
R9
D4
I/O
32 bits data bus
R10
GPSRAM1
O
Not used (Fixed to “H”)
R11
D3
I/O
32 bits data bus
R12
DQM3
O
Data enable output for SDRAM
R13
CAS
O
Column address select output for SDRAM
R14
SDWE
O
Write enable output for SDRAM
R15
AVDD1
—
2.9V DC input
