49
PEGA-CC5
Pin No.
Pin Name
I/O
Description
161
NC
—
Not used
162
CS0
O
Chip select signal output to the ASIC
163
RD
O
Data read enable signal output to the ASIC
164
VSS
—
Ground terminal
165
VDD
—
Power supply terminal (+3.3V)
166
DGRNT
O
Enable signal output of external test logic or bus master Not used
167
DREQ
I
Arbitration request signal input terminal
168
ALE
O
Address latch signal (upper byte) output to the ASIC
169
WE
O
Write enable signal output to the ASIC and SD-RAM
170
VDD
—
Power supply terminal (+3.3V)
171, 172
A12, A11
O
Address signal output to the ASIC, flash memory and SD-RAM
173
VSS
—
Ground terminal
174, 175
A10, A9
O
Address signal output to the ASIC, flash memory and SD-RAM
176
VDD
—
Power supply terminal (+3.3V)
177, 178
A8, A7
O
Address signal output to the ASIC, flash memory and SD-RAM
179
VSS
—
Ground terminal
180, 181
A6, A5
O
Address signal output to the ASIC, flash memory and SD-RAM
182
VDD
—
Power supply terminal (+3.3V)
183
A4
O
Address signal output to the ASIC, flash memory and SD-RAM
184
VSS
—
Ground terminal
185, 186
A3, A2
O
Address signal output to the ASIC, flash memory and SD-RAM
187
VDD
—
Power supply terminal (+3.3V)
188, 189
A1, A0
O
Address signal output to the ASIC, flash memory and SD-RAM
190, 191
VSS
—
Ground terminal
192
DCS0
O
Chip select signal output to the SD-RAM
193
RAS1
O
Row address strobe signal output terminal
194
RAS0
O
Row address strobe signal output to the SD-RAM
195
CAS0
O
Column address strobe signal output to the SD-RAM
196
VDD
—
Power supply terminal (+3.3V)
197
CAS1
O
Column address strobe signal output to the SD-RAM
198
CAS2
O
Column address strobe signal output terminal
199
CAS3
O
Column address strobe signal output to the SD-RAM
200
VSS
—
Ground terminal
201
VDD
—
Power supply terminal (+3.3V)
202
DCKE
O
Clock enable signal output to the SD-RAM
203
VSS
—
Ground terminal
204
DCLKIN
I
Clock signal input terminal
205
DCLKOUT
O
Clock signal output to the ASIC and SD-RAM
206
VDD
—
Power supply terminal (+3.3V)
207
DQML
O
Write mask signal output to the SD-RAM (lower byte)
208
DQMH
O
Write mask signal output to the SD-RAM (upper byte)
Summary of Contents for PEGA-CC5
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