55
Pin No.
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98 to 100
101
102
103
104 to 106
107
108
109
110 to 112
113
126,127
128
129
133
134
136
138
I/O
I/O
-
I/O
O
O
-
O
-
O
O
O
-
O
-
O
-
O
-
O
-
O
-
O
-
O
-
O
-
O
-
O
-
O
O
I/O
I/O
-
-
I/O
Description
Memory address.
Ground for core logic and I/O signals.
Memory address.
SDRAM LDQM.
SDRAM UDQM.
3.3-V supply voltage for core logic and I/O signals.
SDRAM/EDO write enable. Decoder asserts active LOW to request a write operation to the SDRAM array.
Ground for core logic and I/O signals.
SDRAM system cclock.
Active LOW SDRAM column address.
Active LOW SDRAM row address.
3.3-V supply voltage for core logic and I/O signals.
Active LOW SDRAM bank select.
Ground for core logic and I/O signals.
Active LOW SDRAM bank select.
3.3-V supply voltage for core logic and I/O signals.
Active LOW EDO DRAM column address strobe.
Ground for core logic and I/O signals.
Active LOW EDO DRAM Row address strobe.
3.3-V supply voltage for core logic and I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
3.3-V supply voltage for core logic and I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
3.3-V supply voltage for core logic and I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
3.3-V supply voltage for core logic and I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
3.3-V supply voltage for core logic and I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
3.3-V supply voltage for core logic and I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
ROM chip select. Open drain signal, must be pulled-up to 3.3 volts.
Programmable I/O pins.
Programmable I/O pins.
3.3-V supply voltage for core logic and I/O signals.
Ground for core logic and I/O signals.
Programmable I/O pins.
Pin Name
MDATA[15:0]
VSS
MDATA[15:0]
LDQM
UDQM
VDD
MWE
VSS
SD-CLK
SD-CAS
SD-RAS
VDD
SD-CS[1:0]
VSS
SD-CS[1:0]
VDD
EDO-CAS
VSS
EDO-RAS
VDD
MADDR[20:0]
VSS
MADDR[20:0]
VDD
MADDR[20:0]
VSS
MADDR[20:0]
VDD
MADDR[20:0]
VSS
MADDR[20:0]
VDD
MADDR[20:0]
ROM-CS
PIO[10:0]
PIO[10:0]
VDD
VSS
PIO[10:0]
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