54
Pin No.
1
2 to 4
5
6
7
8 to 11
12
13
14
15
16
17
19
27
29
36
38
40
42
47
49
52
53,54
67
68
69
70
71
72 to 74
75
I/O
I/O
I/O
-
I/O
-
I/O
-
I
-
O
O
-
-
-
-
-
-
-
-
-
-
I/O
I/O
-
I/O
-
I/O
-
I/O
-
Description
Programmable I/O pins.
8bit bl-directional host data bus. Host writes data to the decoder Code FIFO via HDATA[7:0]. MSB of the 32-bit
word is written first. The host also reads and writes the decoder internal registers and local SDRAM/ROM via
HDATA[7:0].
3.3-V supply voltage for core logic and I/O signals.
8bit bl-directional host data bus. Host writes data to the decoder Code FIFO via HDATA[7:0]. MSB of the 32-bit
word is written first. The host also reads and writes the decoder internal registers and local SDRAM/ROM via
HDATA[7:0].
Ground for core logic and I/O signals.
8bit bl-directional host data bus. Host writes data to the decoder Code FIFO via HDATA[7:0]. MSB of the 32-bit
word is written first. The host also reads and writes the decoder internal registers and local SDRAM/ROM via
HDATA[7:0].
3.3-V supply voltage for core logic and I/O signals.
Hardware reset. An external device asserts RESET (active LOW) to execute a decoder hardware reset. To ensure
proper initialization after power in stable, assert RESET for at least 20Ms.
Ground for core logic and I/O signals.
Active LOW to indicate host initiated transfer is not complete. WAIT is asserted after the falling edge of CS and
reasserted when decoder is ready to complete transfer cycle. Open drain signal, must be pulled-up to 3.3 volts.
Driven high for 10 ns before tristate.
Host interrupt. Open drain signal, must be pulled-up to 3.3 volts. Driven high for 10 ns before tristate.
3.3-V supply voltage for core logic and I/O signals.
Ground for core logic and I/O signals.
3.3-V supply voltage for core logic and I/O signals.
Ground for core logic and I/O signals.
3.3-V supply voltage for core logic and I/O signals.
Ground for core logic and I/O signals.
3.3-V supply voltage for core logic and I/O signals.
Ground for core logic and I/O signals.
3.3-V supply voltage for core logic and I/O signals.
Ground for core logic and I/O signals.
Programmable I/O pins.
Memory address.
3.3-V supply voltage for core logic and I/O signals.
Ground for core logic and I/O signals.
3.3-V supply voltage for core logic and I/O signals.
Ground for core logic and I/O signals.
3.3-V supply voltage for core logic and I/O signals.
Ground for core logic and I/O signals.
Memory address.
3.3-V supply voltage for core logic and I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
3.3-V supply voltage for core logic and I/O signals.
Pin Name
PIO[10:0]
HDATA[7:0]
VDD
HDATA[7:0]
VSS
HDATA[7:0]
VDD
RESET
VSS
WAIT
INT
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
PIO[10:0]
MDATA[15:0]
VSS
MDATA[15:0]
VDD
MDATA[15:0]
VSS
MDATA[15:0]
VDD
VIDEO BOARD IC506 CL8830-PDQ (MPEG VIDEO/AUDIO DECODER, VIDEO SIGNAL PROCESSOR)
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