57
Pin No.
190
193
195
197
199
202 to 204
206
207
208
I/O
I/O
-
-
-
-
I
I
I
I
Description
Programmable I/O pins.
3.3-V supply voltage for core logic and I/O signals.
Ground for core logic and I/O signals.
3.3-V supply voltage for core logic and I/O signals.
Ground for core logic and I/O signals.
Host address bus. 3-bit address bus selects one of eight host interface registers.
Host chip select. Host asserts CS to select the decoder for a read or write operation. The falling edge of this signal
triggers the read of write operation.
Read/write strobe in M mode. Write strobe in I mode. Host asserts R/W LOW to select write and LOW to select Read.
Read strobe in I mode. Must be held HIGH in M Mode.
Pin Name
PIO[10:0]
VDD
VSS
VDD
VSS
HADDR[2:0]
CS
R/W
RD
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