Sony DXC-390, Service Manual, Page: 76 / 110

6-4
DXC-390/390P
IC
CXD1256AR (SONY)
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16
TIMING GENERATOR FOR CCD CAMERA
—TOP VIEW—
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
O
I
I
I
I
I
I
—
I
O
I
I
I
I
O
O
OSCO
OSCI
EF
ED0
ED1
ED2
SMD1
GND
SMD2
VCT
D1
D2
D3
D4
A5
A4
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
O
O
O
O
—
O
O
—
—
O
O
—
O
O
O
O
A3
A0
A1
A2
GND
RG
LH1
V
CC
V
CC
H1
H2
GND
SUB
V2
V1
SG1
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
O
O
O
I
O
O
O
—
O
O
O
O
O
O
O
O
V3
SG2
V4
TEST2
MCK
SHP
SHD
GND
SP1
SP2
SH1
SH2
DL1
DL2
BFG
CLP1
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
I/O
I/O
O
O
O
O
I
—
O
I
I
I
I
I
O
I
CLP2
CLP3
CLP4
PBLK
ID
WEN
GM
V
CC
CL
PS
HD
VD
HTSG
TEST
CK
CK
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
INPUTS
CK
D1
D2
D3
D4
ED0 - ED2
EF
GM
HD
HTSG
OSCI
PS
SMD1, SMD2
VD
OUTPUTS
A0 - A5
BFG
CK
CL
CLP1, CLP4
DL1
,
DL2
H1, H2
ID
MCK
OSCO
PBLK
RG
SG1
,
SG2
SH1
,
SH2
SHD,
SHD
SHP,
SHP
SP1
,
SP2
SUB
V1
-
V4
VCT
WEN
INPUT/OUTPUT
CLP2, CLP3
OTHER
TEST, TEST2
: NTSC (1820 fH)/PAL (1816 fH) CLOCK
: NORMALLY FIX TO “LOW” LEVEL
:
COLOR
/BW SELECT
:
FIELD
/FRAME SELECT
:
NTSC
(EIA) /PAL (CCIR) SELECT
: SHUTTER SPEED SETTING
: (NOT IN USE)
:
ANALOG PROCESSING
/DIGITAL PROCESSING
: HORIZONTAL SYNC
: XSG1, XSG2 CONTROL
: INVERTER FOR OSCILLATOR
: SHUTTER SPEED SELECT (
SERIAL
/PARALLEL)
: SHUTTER MODE SETTING
: VERTICAL SYNC
: (NOT IN USE)
: ENCODER/CHROMA MODULATOR PULSE
: NTSC (1820 fH)/PAL (1816 fH) CLOCK
: NTSC (910 fH)/PAL (908 fH) CLOCK
: CLAMP PULSE
: CLOCK FOR DELAY LINE
: CCD HORIZONTAL REGISTER DRIVE CLOCK
: LINE IDENTIFICATION
LH1 : CLOCK FOR LAST CCD VERTICAL REGISTER
: NTSC (910 fH)/PAL (908 fH) CLOCK
: INVERTER FOR OSCILLATOR
: BLANKING CLEANING PULSE
: RESET GATE PULSE
: CCD ELECTRIC CHARGE READ OUT PULSE
: SELECTION
: DATA S/H PULSE
: PRE-CHARGE LEVEL S/H PULSE
: COLOR SEPARATION S/H PULSE
: CCD ELECTRIC CHARGE SUBSTRATE PULSE
: CCD VERTICAL REGISTER DRIVE CLOCK
: (NOT IN USE)
: WRITE ENABLE
: CLAMP PULSE
: TEST
HIGH PULSE
GENERATOR
CIRCUIT
ADR. COUNT
1/2
H ROM
LATCH
ADR. COUNT
V ROM
LATCH
GATE
DRIVER
GATE CONTROL
GATE COUNTER DECODER
SHUT
ROM
ADR. COUNT
ROG ROM
LATCH GATE
DECODE
VD
INITIALIZE
MODE
SET
HD
INITIALIZE
SP1
,
SP2
41, 42
SH1
SH2
DL1
,
DL2
RG
MCK
SHP
SHD
43
44
45, 46
22
37
38
39
VD
60
HD
59
CK
63
CK
64
CL
57
SG1
,
SG2
32, 34
HTSG
61
V1
-
V4
30, 31, 33, 35
ED0 - ED2
4 - 6
7, 9
58
SMD1, SMD2
PS
D1 - D4
11 - 14
EF
A0 - A5
GM
OSCO
3
15 - 20
55
1
OSCI
2
VCT
10
BFG
CLP1, CLP4
CLP2, CLP3
PBLK
ID
47
48, 51
49, 50
52
53
H1, H2
26, 27
LH1
23