DSX-M50BT
26
Pin No.
Pin Name
I/O
Description
78, 79
VVDD2, VVDD3
-
Power supply terminal (+3.3V) (for PLL)
80
DVSS
-
Ground terminal (for digital system)
81
DVDD
-
Power supply terminal (+3.3V) (for digital system)
82
CP-SCL
O
Serial data transfer clock signal output to the EEPROM
83
CP-SDA
I/O
Two-way serial data bus with the EEPROM
84
CP-nRES
O
Reset signal output terminal Not used
85
NC
-
Not used
86
CMDERR
O
Command error signal output to the system controller “H”: error
87
TEST0 (GND)
I
Test mode setting terminal Fixed at “L”
88
DVDD
-
Power supply terminal (+3.3V) (for digital system)
89
DVSS
-
Ground terminal (for digital system)
90
DVDD15
-
External capacitor connection terminal for internal regulator
91
JTRSTB (IPD)
I
Reset signal input terminal (for JTAG) Normally:
fi
xed at “L”
92
JTCK (IPD)
I
Clock signal input terminal (for JTAG) Normally:
fi
xed at “L”
93
JTDI (IPD)
I
Data input terminal (for JTAG) Normally:
fi
xed at “L”
94
JTMS (IPU)
I
Mode selection signal input terminal (for JTAG) Normally:
fi
xed at “H”
95
JTDO (O)
O
Data output terminal (for JTAG) Normally: open
96
JTRTCK (O)
O
Return clock signal output terminal (for JTAG) Normally: open
97
TEST1 (GND)
I
Test mode setting terminal Fixed at “L”
98
AVDD1
-
Power supply terminal (+3.3V) (for A/D converter)
99
AVSS1
-
Ground terminal (for A/D converter)
100
LRREF
-
External capacitor connection terminal for audio D/A converter and electrical volume reference
voltage
Summary of Contents for DSX-M50BT
Page 12: ...DSX M50BT 12 MEMO ...
Page 33: ...MEMO DSX M50BT 33 ...
