Sony CDL1100, Service Manual

Page: 26 / 89

7-4
TMAX detection result
Longer than ref. period
Shorter than ref. period
Within ref. period
TMAX output
P2VREF
VSS
HiZ
Ground
Bit clock output (1.4122MHz)
Audio data output
Digital output (Not used)
Buffer memory over signal otuput “H”: at over
Outputs the correction flag. This pin becomes “H” when the AOUT output cannot be
corrected in the C2 correction
Outputs the CRCC judging result of subcode Q data. This pin becomes “H” when the
judging result is OK (Not used)
Inputs the clock for subcode P-W data reading selectable by command bit
+5V power supply
Ground
Subcode P-W data output
Frame sync signal output (Signal in regeneration system)
Subcode block sync signal output. “H” at S1 position when subcode sync is detected
Clock output for processor status signal reading (176.4kHz) (Not used)
Processor status signal output (Not used)
Output the frame clock in the correction system (7.35MHz) (Not used)
LSI internal monitoring signal output. DSP internal flag and PLL clock can be monitored
by microcomputer commands (Not used)
+5V power supply
Test pin (Fixed at “L”)
Reference voltage input for PLL (+4.2V)
VCO center frequency shift signal output
Outputs of phase error between EFM signal and PLCK signal (Used in x8 speed mode)
Outputs of phase error diference signal between EFM signal and PLCK signal
TMAX detection result signal output (Select by command bit TMPS) *1
TMAX detection result signal output (Select by command bit TMPS)
Inverted amplifier input for low-pass filter
Amplifier output for low-pass filter
Reference voltage input for PLL (+2.1V)
VCO center frequency reference level input (Fixed at “PVREF”)
Output from VCO filter
Ground (Analog)
Data slice level signal output
RF signal input
+5V power supply (Analog)
RFRP signal center level input
RFRP zero crossing input
RF ripple signal input
Focus error signal input
Sub beam adding signal input
Test pin (Fixed at “VREF”)
—
O
O
O
O
O
O
I/O
—
—
O
O
O
O
O
O
O
—
—
I
O
O
O
O
O
I
O
I
I
O
—
O
I
—
I
I
I
I
I
I
VSS
BCK
AOUT
DOUT
MBOV
IPF
SBOK
CLCK
VDD
VSS
DATA
SFSY
SBSY
SPCK
SPDA
COFS
MONIT
VDD
TESIO0
P2VREF
SPDO
PDOS
PDO
TMAXS
TMAX
LPFN
LPFO
PVREF
VCOREF
VCOF
AVSS
SLCO
RFI
AVDD
RFCT
RFZI
RFRP
FEI
SBAD
TSIN
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• IC105 Digital Servo & Digital Signal Processor (TC9439F) / MA-C22 board
Function Pin No. Pin Name I/O
*1