Sony BKP-5090, Installation And Maintenance Manual

Page: 109 / 138

6-17
BKP-5090
IC
TLC0820ACDW (TI)FLAT PACKAGE
TLC0820ACDWR
V
DD
NC
ANLG
IN
OUT
D1
OUT
D2
OUT
D3
OUT
WR
/RDY
IN/OUT
MODE
IN
1
2
3
4
5
6
7
D0
(LSB)
RD
IN
8
14
15
16
17
18
19
20
13
GND
12
11
1
2
3
4
REF +
REF _
ANLG
7
MODE
13
CS
8
RD
6
WR
/RDY
(LSB)D0
D1
D2
D3
D4
D5
D6
(MSB)D7
OFLW
OUT
OFLW
INT
D7
OUT
(MSB)
INPUT
ANLG
CS
MODE
RD
REF + , REF _
: ANALOG SIGNAL
: CHIP SELECT
: MODE
: READ
: REFERENCE VOLTAGE + , _
OUTPUT
D0 - D7
INT
OFLW
INPUT/OUTPUT
WR
/RDY
: DIGITAL SIGNAL
: INTERRUPT
: OVERFLOW
: L : WRITE/H : READY
D6
OUT
D5
OUT
D4
OUT
CS
IN
REF +
IN
REF _
IN
INT
OUT 9 12
10 11
5
14
15
16
17
18
9
C-MOS 8-BIT SEMIFLASH TYPE A/D CONVERTER
4-BIT FLASH
A/D CONVERTER
(HIGHER)
4
OUTPUT
LATCH
AND
3-STATE
BUFFER
TIMING
&
CONTROL
4-BIT FLASH
A/D CONVERTER
(LOWER)
_ 1
+
1
REF +
REF _
ANLG
12
11
1
7
13
8
6
9
MODE
CS
RD
WR/RDY
INT
18
OFLW
4-BIT
D/A CONVERTER
17
D7(MSB)
16
D6
15
D5
14
D4
5
D3
4
D2
3
D1
2
D0(LSB)
4
4
4
UPD4702G (NEC)
V
DD
1
2
3
4
5
6
7
RESET
A
B
CD0
CD1
CD2
CD3 CD5
CD4
A
OE
CD6
CD7
OE
STB
BORROW
CARRY
8
14
15
16
17
18
19
20
13
A
B
BORROW
CARRY
CD0 - 7
OE
RESET
STB
: INCREMENTAL SIGNAL (PHASE A) INPUT
: INCREMENTAL SIGNAL (PHASE B) INPUT
: BORROW PULSE OUTPUT
: CARRY PULSE OUTPUT
: COUNT DATA OUTPUT
: OUTPUT CONTROL SIGNAL INPUT
: COUNTER RESET INPUT
: LATCH STROBE SIGNAL INPUT
NC
NC
NC
GND
16
2
B
3
RESET
1
18
5
6
7
8
12
13
14
15
CD0
CD1
CD2
CD3
CD4
CD5
CD6
CD7
BORROW
CARRY
9 12
10 11
STB
17 19
A
2
RESET
5-8
12-15
19
18
1
B
3
OE
16
CD0 - CD7
CARRY
BORROW
STB
17
PHASE
DISCRIMINATION
EDGE DETECTOR
8-BIT
UP/DOWN COUNTER
8-BIT LATCH
TRI-STATE OUTPUT
C-MOS INCREMENTAL ENCODER 8-BIT UPDOWN COUNTER
—TOP VIEW—
UPD71055GB-10-3B4 (NEC)
V
DD
1
2
3
4
5
6
7
CS
A1
A0
P27
P26
P25
P24
P20
P21
P22 P23 P10 P11 P12 P13 P14 P15 P16 P17
RD
P00 P01 P02 P03 P04 P05 P06 P07
WR
IC
8 26
27
28
29
30
31
32
25
GND
43
42
41
35
44
32
RESET
RESET
31
D0
D0
30
D1
D1
29
D2
D2
28
D3
D3
27
D4
D4
26
D5
D5
25
D6
D6
24
D7
D7
4
WR
RD
A0
CS
A1
5
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
A1, A0
CS
D7 - D0
P07 - P00
IC
CS
0
0
0
0
0
0
0
0
0
0
1
RD
0
0
0
0
0
1
1
1
1
1
X
WR
1
1
1
1
0
0
0
0
0
1
X
A1
0
0
1
1
X
0
0
1
1
X
X
A0
0
1
0
1
X
0
1
0
1
X
X
OPERATION
PORT0
→
DATA • BUS
PORT1
→
DATA • BUS
PORT2
→
DATA • BUS
DATA • BUS
→
PORT0
DATA • BUS
→
PORT1
DATA • BUS
→
PORT2
DATA • BUS
→
COMMAND REGISTER
0
1
X
: LOW LEVEL
: HIGH LEVEL
: DON’T CARE
CPU ACTION
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
DISABLE
HIGH IMPEDANCE
P17 - P10
P27 - P20
RD
WR
; ADDRESS
; CHIP SELECT
; DATA BUS
; PORT 0
; INTERNALLY CONNECTED
; PORT 1
; PORT 2
; READ STROBE
; WRITE STROBE
33
9
24 10
23
NC
NC
NC
INDEX
11
12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34
40
39
38
37
36
14
15
16
18
19
20
21
22
10
11
12
13
9
8
7
6
2
C-MOS PARALLEL INTERFACE UNIT
—TOP VIEW—
PORT 1
PORT 2
PORT 0
READ/
WRITE
CONTROL
DATA BUS
BUFF
8
8
8
8
GROUP
CONTROL
GROUP
CONTROL
COMMAND
REGISTER
13 - 10
6 - 9
24 - 31
44
35
4
5
32
2
36 - 43
22 - 18,
16 - 14
P17 - P10
P23 - P20
P27 - P24
P07 - P00
D7 - D0
RD
WR
A1
A0
RESET
CS
INTERNAL 8-BIT BUS
TL084CPW-E05
TL084CPW-E20 (TI)FLAT PACKAGE
V
EE
V
CC
1 2 3 4 5 6 7
8 9 10 11 12 13 14
+
+
+
+_
_ _
_
OPERATIONAL AMPLIFIER
(J FET INPUT)
—TOP VIEW—