K630 - V640 - K660
1215-3608 rev. 1
FUNCTIONAL OVERVIEW
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Digital Baseband Controller (CPU)
D2000 (Anja)
This component is not replaceable on SL 4 because Baseband calibration is required.
The Digital Baseband Controller is divided in two subsystems:
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Application
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Access
Access Subsystem
All modem functionality in the digital baseband controller resides in the Access
subsystem. This includes EDGE/GPRS/GSM interface, WCDMA interface, USB, and other
peripheral modules. The control CPU is an ARM926 and a DSP is used for signal processing and
layer one control code. The main communication between the blocks in the Access subsystem is
done through the Advanced High-performance bus (AHB) matrix, which is a set of control buses
connecting the different parts together. A block called Syscon is responsible for distributing
clocks and resets to all parts of the Access subsystem. This block is under SW control. The
Access subsystem is connected to the Shared EMIF, an interface for communication with an
external SDRAM. The interface has 39 signals (including one chip select) and supports memory
sizes up to 512 Mbit. The Shared EMIF is shared between the Access subsystem and the
Application subsystem.
Application Subsystem
The Application subsystem contains functionality related to functions such as MMI,
graphics, audio and memory media. The control CPU is an ARM926 with three external
memory interfaces, one shared with the Access subsystem and two dedicated for the
Application subsystem. The Application subsystem contains several blocks. The main
communication between the blocks is done through the Advanced High performance bus (AHB)
matrix, which is a set of control buses connecting the different parts. A block called Syscon is
responsible for distributing clocks and resets to all parts of the Application subsystem. This
block is under SW control. The Application subsystem is connected to the Shared EMIF that is
used for code execution or data storage. In addition, a dedicated EMIF and a Flash IF are also
available. The Application EMIF is a general interface for communication with, for example
external SDRAM, PSRAM, NOR flash, NAND flash and companion chips. The Application EMIF
has a total of 56 signals (including a maximum of 7 chip selects if GPIO is used) and can
be set in several different modes to support different types of memory combinations.
Functional blocks of the Digital Baseband Controller
Keypad
The keypad interface block supports up to 30 keys with 65 columns and 6 rows and operates in
both scan and idle mode. The keypad scan is performed by software. Any transition in the state
of the column inputs is written directly to the register. The keypad interface differentiates
between single key presses, simultaneous presses of any keys with a function key, and any key
releases. The period between successive scans is programmable over the range 5 ms to 80 ms,
in 5 ms steps. During scan mode, the keypad generates an interrupt whenever a valid keypad
state change occurs (including a release of any pressed keys). The scan function is disabled
during system power-up. The keypad is able to detect at least four simultaneous key presses.
Not all combinations are supported.
Technical Description
SEMC Troubleshooting Manual
70
(96)
