SN8P26L38
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 90
Version 1.5
8.3.3 T1CH, T1CL COUNTING REGISTER
T1C is an 16-bit counter register for T1 interval time control. T1CH is high byte of T1C. T1CL is low byte of T1C.
0A1H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T1CL
T1CL7
T1CL6
T1CL5
T1CL4
T1CL3
T1CL2
T1CL1
T1CL0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
0A2H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T1CH
T1CH7
T1CH6
T1CH5
T1CH4
T1CH3
T1CH2
T1CH1
T1CH0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
The equation of T1C [T1CH, T1CL] initial value is as following.
T1C initial value = 65536 - (T1 interrupt interval time * input clock)
Example: To set 10ms interval time for T1 interrupt. High clock is external 4MHz. Fcpu=Fosc/4. Select
T1RATE=010 (Fcpu/64).
T1C initial value = 65536 - (T1 interrupt interval time * input clock)
= 65536 - (10ms * 4MHz / 4 / 64)
= 65536 - (10
-2
* 4 * 10
6
/ 4 / 64)
= 65380
= FF64H ;T1CH=0xFF, T1CL=0x64
The basic timer table interval time of T1.
T1RATE
T1CLOCK
High speed mode (Fcpu = 4MHz / 4)
Low speed mode (Fcpu = 32768Hz / 4)
Max overflow interval One step = max/256
Max overflow interval
One step = max/256
000
Fcpu/256
16.777 s
256 us
2048 s
31250 us
001
Fcpu/128
8.388 s
128 us
1024 s
15625 us
010
Fcpu/64
4.194 s
64 us
512 s
7812.5 us
011
Fcpu/32
2.097 s
32 us
256 s
3906.25 us
100
Fcpu/16
1.048 s
16 us
128 s
1953.125 us
101
Fcpu/8
524.288 ms
8 us
64 s
976.563 us
110
Fcpu/4
262.144 ms
4 us
31 s
488.281 us
111
Fcpu/2
131.072 ms
2 us
16 s
244.141 us
