SN8P26L38
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 113
Version 1.5
10.2.4 IRD IR DUTY CONTROL REGISTER
The IR signal is duty changeable by IRD. IRD decides the IR output signal low pulse width length. When IRC=IRD, the
IR signal changes from high pulse to low pulse. The low pulse stops when IRC overflow. The high pulse width is
IRD-IRR, and the low pulse width is 256-IRD. It is easy to modulate IR duty/cycle by IRR and IRD registers.
0E8H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRD
IRD7
IRD6
IRD5
IRD4
IRD3
IRD2
IRD1
IRD0
Read/Write
W
W
W
W
W
W
W
W
After reset
0
0
0
0
0
0
0
0
The equation of IRD initial value is as following.
IRD initial value = IRR + (256-IRR) / (1/IR duty)
Example: Set IRD for 38KHz IR and duty is 1/3. Input clock is 4MHz.
IRD initial value = IRR + (256-IRR) / (1/IR duty)
IRR of 38KHz = 151
IRD = 151 + (256-151)/(1/ (1/3))
= 186
= BAh
Common IR signal table. System clock is 4MHz.
IR Freq.
(KHz)
IRC
IRR
IRD
Freq. Error
Rate
1/2 duty
1/3 duty
1/4duty
DEC
HEX
DEC
HEX
DEC
HEX
DEC
HEX
32
131
83
193.50
C1
172.67
AC
162.25
A2
0.00%
36
145
91
200.50
C8
182.00
B6
172.75
AC
0.10%
38
151
97
203.50
CB
186.00
BA
177.25
B1
0.25%
39.2
154
9A
205.00
CD
188.00
BC
179.50
B3
0.04%
40
156
9C
206.00
CE
189.33
BD
181.00
B5
0.00%
56
185
B9
220.50
DC
208.67
D0
202.75
CA
0.60%
