SN8P2318 Series
C-type LCD, RFC 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 92
Version 1.5
8.4.4 T1CH, T1CL 16-bit COUNTING REGISTERS
T1 counter is 16-bit counter combined with T1CH and T1CL registers. When T1 timer overflow occurs, the T1IRQ flag
is set as “1” and cleared by program. The T1CH, T1CL decide T1 interval time through below equation to calculate a
correct value. It is necessary to write the correct value to T1CH and T1CL registers, and then enable T1 timer to make
sure the fist cycle correct. After one T1 overflow occurs, the T1CH and T1CL registers are loaded correct values by
program.
0A1H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T1CL
T1CL7
T1CL6
T1CL5
T1CL4
T1CL3
T1CL2
T1CL1
T1CL0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
0A2H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T1CH
T1CH7
T1CH6
T1CH5
T1CH4
T1CH3
T1CH2
T1CH1
T1CH0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After Reset
0
0
0
0
0
0
0
0
The T1 timer counter length is 16-bit and points to T1CH and T1CL registers. The timer counter is double buffer design.
The core bus is 8-bit, so access 16-bit data needs a latch flag to avoid the transient status affect the 16-bit data
mistake occurrence. Under write mode, the write T1CH is the latch control flag. Under read mode, the read T1CL is the
latch control flag. So, write T1 16-bit counter is to write T1CH first, and then write T1CL. The 16-bit data is written to
16-bit counter buffer after executing writing T1CL. Read T1 16-bit counter is to read T1CL first, and then read T1CH.
The 16-bit data is dumped to T1CH, T1CL registers after executing reading T1CL.
Read T1 counter buffer sequence is to read T1CL first, and then read T1CH.
Write T1 counter buffer sequence is to write T1CH first, and then write T1CL.
The equation of T1 16-bit counter (T1CH, T1CL) initial value is as following.
T1CH, T1CL initial value = 65536 - (T1 interrupt interval time * T1 clock rate)
Example: To calculation T1CH and T1CL values to obtain 500ms T1 interval time. T1 clock source is Fcpu
= 16MHz/16 = 1MHz. Select T1RATE=000 (Fcpu/128).
T1 interval time = 500ms. T1 clock rate = 16MHz/16/128
T1 16-bit counter initial value = 65536 - (T1 interval time * input clock)
= 65536 - (500ms * 16MHz / 16 / 128)
= 65536 - (500*10
-3
* 16 * 10
6
/ 16 / 128)
= F0BDH
(T1CH = F0H, T1CL = BDH)
