SONIX SN8P2308 User Manual Download Page 41 | Manualshive

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SN8P2318 Series

C-type LCD, RFC 8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD

Page 41

Version 1.5

The LVD (low voltage detector) is built-in Sonix 8-bit MCU to be brown out reset protection. When the VDD drops and
is below LVD detect voltage, the LVD would be triggered, and the system is reset. The LVD detect level is different by
each MCU. The LVD voltage level is a point of voltage and not easy to cover all dead-band range. Using LVD to
improve brown out reset is depend on application requirement and environment. If the power variation is very deep,
violent and trigger the LVD, the LVD can be the protection. If the power variation can touch the LVD detect level and
make system work error, the LVD can

’t be the protection and need to other reset methods. More detail LVD information

is in the electrical characteristic section.
The LVD is three levels design (2.0V/2.4V/3.6V) and controlled by LVD code option. The 2.0V LVD is always enable for
power on reset and Brown Out reset. The 2.4V LVD includes LVD reset function and flag function to indicate VDD
status function. The 3.6V includes flag function to indicate VDD status. LVD flag function can be an

easy low battery

detector

. LVD24, LVD36 flags indicate VDD voltage level. For low battery detect application, only checking LVD24,

LVD36 status to be battery status. This is a cheap and easy solution.

086H

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PFLAG

NT0

NPD

LVD36

LVD24

-

C

DC

Z

Read/Write

R/W

R/W

R

R

-

R/W

R/W

R/W

After reset

-

-

0

0

-

0

0

0

Bit 5

LVD36:

LVD 3.6V operating flag and only support LVD code option is LVD_H.

0 = Inactive (VDD > 3.6V).

1 = Active (VDD

≦

3.6V).

Bit 4

LVD24:

LVD 2.4V operating flag and only support LVD code option is LVD_M.

0 = Inactive (VDD > 2.4V).

1 = Active (VDD

≦

2.4V).

LVD

LVD Code Option

LVD_L

LVD_M

LVD_H

LVD_MAX

2.0V Reset

Available

Available

Available

Available

2.4V Flag

-

Available

-

-

2.4V Reset

-

-

Available

-

3.6V Flag

-

-

Available

-

3.6V Reset

-

-

-

Available

LVD_L

If VDD < 2.0V, system will be reset.
Disable LVD24 and LVD36 bit of PFLAG register.

LVD_M

If VDD < 2.0V, system will be reset.
Enable LVD24

bit of PFLAG register. If VDD > 2.4V, LVD24 is “0”. If VDD

≦

2.4V, LVD24 flag is “1”.

Disable LVD36 bit of PFLAG register.

LVD_H

If VDD < 2.4V, system will be reset.
Enable LVD24 bit of PFLAG register. If VDD > 2.4V, LVD24 is “0”. If VDD

≦

2.4V, LVD24 flag is “1”.

Enable LVD36 bit of PFLAG register. If VDD > 3.6V,

LVD36 is “0”. If VDD

≦

3.6V, LVD36 flag is “1”.

LVD_MAX

If VDD < 3.6V, system will be reset.



Note:

1. After any LVD reset, LVD24, LVD36 flags are cleared.

2. The voltage level of LVD 2.4V or 3.6V is for design reference only. Don

’t use the LVD indicator as

precision VDD measurement.

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Summary of Contents for SN8P2308

Page 1: ...ded or authorized for us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failur...

Page 2: ...dify CHARACTERISTIC GRAPHS Chapter VER 1 1 May 2011 1 Modify Chapter 6 10 T1 INTERRUPT OPERATION description Example T1 interrupt service routine T1CL read first 2 Modify Chapter 13 2 description It i...

Page 3: ...2 2 1 3 BIT DEFINITION of SYSTEM REGISTER 23 2 2 2 ACCUMULATOR 25 2 2 3 PROGRAM FLAG 26 2 2 4 PROGRAM COUNTER 27 2 2 5 H L REGISTERS 30 2 2 6 Y Z REGISTERS 31 2 2 7 R REGISTER 31 2 3 ADDRESSING MODE 3...

Page 4: ...DE 53 5 1 OVERVIEW 53 5 2 NORMAL MODE 54 5 3 SLOW MODE 54 5 4 POWER DOWN MDOE 54 5 5 GREEN MODE 55 5 6 OPERATING MODE CONTROL MACRO 56 5 7 WAKEUP 57 5 7 1 OVERVIEW 57 5 7 2 WAKEUP TIME 57 5 7 3 P1W WA...

Page 5: ...ENT COUNTER REGISTERS 95 8 4 9 T1 TIMER OPERATION EXAMPLE 96 9 9 9 RESISTANCE TO FREQURNCY CONVERTER RFC 98 9 1 OVERVIEW 98 9 2 RFC APPLICATION CIRCUIT 99 9 3 RFC OPERATION 99 9 4 RFCM REGISTER 100 9...

Page 6: ...SN8P2318 Series C type LCD RFC 8 Bit Micro Controller SONiX TECHNOLOGY CO LTD Page 6 Version 1 5 1 1 16 6 6 PACKAGE INFORMATION 117 16 1 LQFP 64 PIN 117 16 2 LQFP 48 PIN 118...

Page 7: ...D Driver 128 dots supports internal C type Bi directional P0 P1 P5 and external R type bias Bi directional and shared with SEG pins P2 P3 On chip watchdog timer and clock source is Input only shared w...

Page 8: ...T FLO LXIN XOUT FCPUO P0 4 XIN VSS V1 C C V2 VLCD COM0 COM1 COM2 COM3 SEG0 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P0 2 T1IN 1 O 48 SEG1 P0 1 INT1 2 47 SEG2 P0 0 INT0 3 46 SEG3 P1 0 RFC0 4 45...

Page 9: ...1 O 36 COM2 P0 2 T1IN 2 35 COM3 P0 1 INT1 3 34 SEG7 P0 0 INT0 4 33 SEG8 P1 0 RFC0 5 32 SEG9 P1 1 RFC1 6 SN8P2317F 31 SEG10 P1 2 RFC2 7 30 SEG11 P1 3 RFC3 8 29 SEG12 P1 4 RFC4 9 28 SEG13 P1 5 10 27 SEG...

Page 10: ...direction pin Schmitt trigger structure as input mode Built in pull up resisters Level change wake up INT1 External interrupt 1 input pin P0 2 T1IN I O P0 2 Bi direction pin Schmitt trigger structure...

Page 11: ...h Pin PnUR PnM I O Input Bus I O Output Bus PnM Specific Output Function e g PWM RFC shared pin structure Pull Up Resistor Output Latch Pin PnUR PnM Output Bus PnM IO Input Bus Specific Output Functio...

Page 12: ...tal Oscillator output pin FCPUO RC Fcpu signal output pin to measure RC frequency for adjusting RC parameters P0 4 PLL_16M GPIO mode Pull Up Resistor Output Latch Pin PnUR PnM PnM High_Clk Code Option...

Page 13: ...08H Interrupt vector User interrupt vector 0009H General purpose area User program 000FH 0010H 0011H 0FFCH End of user program 0FFDH Reserved 0FFEH 0FFFH The ROM includes Reset vector Interrupt vector...

Page 14: ...reset external reset or watchdog timer overflow reset then the chip will restart the program from address 0000h and all system registers will be set as default values It is easy to know reset status...

Page 15: ...The following example shows the way to define the interrupt vector in the program memory Note PUSH POP instructions save and load ACC PFLAG without NT0 NPD PUSH POP buffer is a unique buffer and only...

Page 16: ...user program User program JMP START End of user program MY_IRQ The head of interrupt service routine PUSH Save ACC and PFLAG register to buffers POP Load ACC and PFLAG register from buffers RETI End...

Page 17: ...1 L To set lookup table1 s low address MOVC To lookup data R 00H ACC 35H Increment the index address for next address INCMS Z Z 1 JMP F Z is not overflow INCMS Y Z overflow FFH 00 Y Y 1 NOP MOVC To lo...

Page 18: ...define a word 16 bits data DW 5105H DW 2012H The other example of look up table is to add Y or Z index register by accumulator Please be careful if carry happen Example Increase Y and Z register by B...

Page 19: ...ad of the ROM boundary B0ADD PCL A PCL PCL ACC PCH 1 when PCL overflow occurs JMP A0POINT ACC 0 jump to A0POINT JMP A1POINT ACC 1 jump to A1POINT JMP A2POINT ACC 2 jump to A2POINT JMP A3POINT ACC 3 ju...

Page 20: ...f the jump table listing is five 0X00FD JMP A0POINT ACC 0 jump to A0POINT 0X00FE JMP A1POINT ACC 1 jump to A1POINT 0X00FF JMP A2POINT ACC 2 jump to A2POINT 0X0100 JMP A3POINT ACC 3 jump to A3POINT 0X0...

Page 21: ...address to end_addr2 CLR Y Set Y to 00H CLR Z Set Z to 00H MOVC B0BSET FC Clear C flag ADD DATA1 A Add A to Data1 MOV A R ADC DATA2 A Add R to Data2 JMP END_CHECK Check if the YZ address the end of co...

Page 22: ...1L STK1H STK0L STK0H 2 2 1 2 SYSTEM REGISTER DESCRIPTION H L Working HL addressing register Y Z Working YZ and ROM addressing register R Working register and ROM look up data buffer PFLAG Special flag...

Page 23: ...DTR7 WDTR6 WDTR5 WDTR4 WDTR3 WDTR2 WDTR1 WDTR0 W WDTR 0CDH TC0R7 TC0R6 TC0R5 TC0R4 TC0R3 TC0R2 TC0R1 TC0R0 W TC0R 0CEH PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 R W PCL 0CFH PC11 PC10 PC9 PC8 R W PCH 0D0H P04 P...

Page 24: ...0PC7 S0PC6 S0PC5 S0PC4 S0PC3 S0PC2 S0PC1 S0PC0 R W STK0L 0FFH S0PC11 S0PC10 S0PC9 S0PC8 R W STK0H Note 1 To avoid system error make sure to put all the 0 and 1 as it indicates in the above table 2 All...

Page 25: ...be access by B0MOV instruction during the instant addressing mode Example Read and write ACC value Read ACC data and store in BUF data memory MOV BUF A Write a immediate data into ACC MOV A 0FH Write...

Page 26: ...1 1 Reset by external Reset Pin Bit 5 LVD36 LVD 3 6V operating flag and only support LVD code option is LVD_H 0 Inactive VDD 3 6V 1 Active VDD 3 6V Bit 4 LVD24 LVD 2 4V operating flag and only suppor...

Page 27: ...Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PC PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 After reset 0 0 0 0 0 0 0 0 0 0 0 0 PCH PCL ONE ADDRESS SKIPPING There are nine...

Page 28: ...S BUF0 JMP C0STEP Jump to C0STEP if ACC is not zero C0STEP NOP INCMS instruction INCMS BUF0 JMP C0STEP Jump to C0STEP if BUF0 is not zero C0STEP NOP If the destination decreased by 1 which results und...

Page 29: ...ue by the three instructions and don t care PCL overflow problem Note PCH only support PC up counting result and doesn t support PC down counting When PCL is carry after PCL ACC PCH adds one automatic...

Page 30: ...2 Bit 1 Bit 0 L LBIT7 LBIT6 LBIT5 LBIT4 LBIT3 LBIT2 LBIT1 LBIT0 Read Write R W R W R W R W R W R W R W R W After reset Example If want to read a data from RAM address 20H of bank_0 it can use indirec...

Page 31: ...0H To set RAM bank 0 for Y register B0MOV Z 25H To set location 25H for Z register B0MOV A YZ To read a data into ACC Example Uses the Y Z register as data pointer to clear the RAM data B0MOV Y 0 Y 0...

Page 32: ...t of ACC Example Move 0x12 RAM location data into ACC B0MOV A 12H To get a content of RAM location 0x12 of bank 0 and save in ACC Example Move ACC data into 0x12 RAM location B0MOV 12H A To get a cont...

Page 33: ...nstruction are executed The STKP register is a pointer designed to point active level in order to push or pop up data from stack buffer The STKnH and STKnL are the stack buffers to store program count...

Page 34: ...ervice routine Stack operation is a LIFO type Last in and first out The stack pointer STKP and stack buffer STKnH and STKnL are located in the system register area bank 0 0DFH Bit 7 Bit 6 Bit 5 Bit 4...

Page 35: ...STK1L 3 1 0 0 STK2H STK2L 4 0 1 1 STK3H STK3L 5 0 1 0 STK4H STK4L 6 0 0 1 STK5H STK5L 7 0 0 0 STK6H STK6L 8 1 1 1 STK7H STK7L 8 1 1 0 Stack Over error There are Stack Restore operations correspond to...

Page 36: ...tch_Dog Always_On Watchdog timer is always on enable even in power down and green mode Enable Enable watchdog timer Watchdog timer stops in power down mode and green mode Disable Disable Watchdog func...

Page 37: ...pin 2 5 5 Security code option Security code option is OTP ROM protection When enable security code option the ROM code is secured and not dumped complete ROM contents 2 5 6 Noise Filter code option...

Page 38: ...ition Description 0 0 Watchdog reset Watchdog timer overflow 0 1 Reserved 1 0 Power on reset and LVD reset Power voltage is lower than LVD detecting level 1 1 External reset External reset pin detect...

Page 39: ...nd the system is reset After watchdog reset the system restarts and returns normal mode Watchdog reset sequence is as following Watchdog timer status System checks watchdog timer overflow status If wa...

Page 40: ...heavy e g driving motor The loading operating induces noise and overlaps with the DC power VDD drops by the noise and the system works under unstable power situation The power on duration and power do...

Page 41: ...gs indicate VDD voltage level For low battery detect application only checking LVD24 LVD36 status to be battery status This is a cheap and easy solution 086H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...

Page 42: ...ly counting until overflow occurrence The overflow signal of watchdog timer triggers the system to reset and the system return to normal mode after reset sequence This method also can improve brown ou...

Page 43: ...level the system keeps reset status and waits external reset pin released System initialization All system registers is set as initial conditions and system is ready Oscillator warm up Oscillator oper...

Page 44: ...circuit and Diode RC reset circuit is necessary to limit any current flowing into reset pin from external capacitor C in the event of reset pin breakdown due to Electrostatic Discharge ESD or Electric...

Page 45: ...f the VDD drops and the voltage lower than reset pin detect level the system would be reset If want to make the reset active earlier set the R2 R1 and the cap between VDD and C terminal voltage is lar...

Page 46: ...sc 16 Noise_Filter Enable Flosc Fcpu Flosc 4 CPUM 1 0 XIN XOUT STPHX HOSC Fcpu Code Option Fosc Fosc CLKMD Fcpu PLL LXIN LXOUT LOSC HOSC High_Clk code option LOSC Low_Clk code option Fhosc External hi...

Page 47: ...r The oscillator bandwidth is 1MHz 10MHz 4 3 2 INTERNAL HIGH SPEED OSCILLATOR The internal high speed oscillator is 16MHz PLL type The accuracy is 2 under commercial condition When the High_Clk code o...

Page 48: ...connects external C capacitor with LXIN pin The capacitance is 27pF 3V and 39pF 5V at 32KHz LXOUT pin outputs Flosc 32KHz signal for adjust the capacitance by RC type 32K X tal The system low speed c...

Page 49: ...ator active When STPHX 1 the external oscillator or internal high speed PLL oscillator are disabled The STPHX function is depend on different high clock options to do different controls PLL_16M STPHX...

Page 50: ...2560 Fhosc Wake up modes External high speed RC modes 32 Fhosc External low speed 32KHz crystal mode 2 14 256 Flosc External low speed RC modes 32 Flosc Internal PLL 16MHz oscillator warm up time is...

Page 51: ...ow Power Down Mode Wake up Timing Wake up Pin Rising Edge Oscillator Fcpu Instruction Cycle Tosp Tost Wake up Pin Falling Edge System inserts into power down mode Edge trigger system wake up Green Mod...

Page 52: ...is depended on oscillator s material factory and architecture The RC type oscillator s start up time is very short and ignored Low Speed Crystal 32K Tost High Speed Crystal Tost High Speed RC Oscilla...

Page 53: ...anging Reset Control Block One of reset trigger sources actives One of reset trigger sources actives One of reset trigger sources actives Operating Mode Clock Control Table Operating Mode Normal Mode...

Page 54: ...tor frequency The program is executed and full functions are controllable The system rate is low speed Flosc 4 The external low speed oscillator actives and the high speed oscillator is controlled by...

Page 55: ...tem inserts into green mode After system wake up from green mode the CPUM1 bit is disabled zero status automatically The program stops executing and full functions are disabled Only the timer with wak...

Page 56: ...SlowMode macro directly Example Switch slow mode to normal mode The external high speed oscillator stops Slow2Normal Declare Slow2Normal macro directly Example Switch normal slow mode to green mode G...

Page 57: ...is no wakeup time because the clock doesn t stop in green mode The wake up time of the external high speed 12M_X tal 4M_C tal crystal type oscillator is as the following The Wakeup time 1 Fhosc 2560 s...

Page 58: ...ollowing The Wakeup time of 32KHz RC type oscillator mode 1 Flosc 288 sec clock start up time The Wakeup time of 32KHz crystal type oscillator mode 1 Flosc 2 14 256 sec clock start up time Example In...

Page 59: ...el changing When wake up pin occurs rising edge or falling edge the system is waked up by the trigger edge The Port 0 and Port 1 have wakeup function Port 0 wakeup function always enables but the Port...

Page 60: ...to normal mode Once interrupt service is executed the GIE bit in STKP register will clear to 0 for stopping other interrupt request On the contrast when interrupt service exits the GIE bit will set t...

Page 61: ...tine instruction RETI is executed 0C9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTEN T1IEN TC0IEN T0IEN P01IEN P00IEN Read Write R W R W R W R W R W After reset 0 0 0 0 0 Bit 0 P00IEN External...

Page 62: ...o the routine corresponding of the interrupt request 0C8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTRQ T1IRQ TC0IRQ T0IRQ P01IRQ P00IRQ Read Write R W R W R W R W R W After reset 0 0 0 0 0 Bi...

Page 63: ...he interrupt requests occurs and the program counter PC points to the interrupt vector ORG 8 and the stack add 1 level 0DFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKP GIE STKPB2 STKPB1 STKPB...

Page 64: ...instructions save and load ACC PFLAG data into buffers and avoid main routine error after interrupt service routine finishing Note PUSH POP instructions save and load ACC PFLAG without NT0 NPD PUSH PO...

Page 65: ...ection matches interrupt edge configuration the trigger edge will be latched and the system executes interrupt service routine fist after wake up 0BFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P...

Page 66: ...p trigger direction the INT1 interrupt request flag INT1IRQ is latched while system wake up from power down mode or green mode by P0 1 wake up trigger System inserts to interrupt vector ORG 8 after wa...

Page 67: ...equest setup Fcpu 4MHz 4 B0BCLR FT0IEN Disable T0 interrupt service B0BCLR FT0ENB Disable T0 timer MOV A 20H B0MOV T0M A Set T0 clock Fcpu 64 MOV A 64H Set T0C initial value 64H B0MOV T0C A Set T0 int...

Page 68: ...ample TC0 interrupt request setup Fcpu 16MHz 16 B0BCLR FTC0IEN Disable TC0 interrupt service B0BCLR FTC0ENB Disable TC0 timer MOV A 20H B0MOV TC0M A Set TC0 clock Fcpu 64 MOV A 64H Set TC0C initial va...

Page 69: ...t request setup B0BCLR FT1IEN Disable T1 interrupt service B0BCLR FT1ENB Disable T1 timer MOV A 20H B0MOV T1M A Set T1 clock Fcpu 32 CLR T1CH CLR T1CL B0BSET FT1IEN Enable T1 interrupt service B0BCLR...

Page 70: ...sers have to check interrupt control bit and interrupt request flag in interrupt routine Example Check the interrupt request under multi interrupt operation ORG 8 Interrupt vector JMP INT_SERVICE INT_...

Page 71: ...de option Reset VPP HV OTP Programming P0 4 I O XOUT AC High_Clk code option 4M 12M FCPUO DC High_Clk code option RC P1 0 I O RFC0 AC RFCENB 1 RFCH 2 0 000b P1 1 I O RFC1 AC RFCENB 1 RFCH 2 0 001b P1...

Page 72: ...1 Bit 0 P2M P27M P26M P25M P24M P23M P22M P21M P20M Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 0C3H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P3M P37M P36M P35M P34M...

Page 73: ...M 0 Set P2 0 to input mode Enable P2 0 P2 7 and P3 0 P3 3 GPIO function B0BCLR FPSEG2 Set PSEG 2 0 011b B0BSET FPSEG1 B0BSET FPSEG0 MOV A 0XFF Set P2 0 P2 7 to output mode B0MOV P2M A MOV A 0X0F Set P...

Page 74: ...0 0E1H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1UR P16R P15R P14R P14R P12R P11R P10R Read Write W W W W W W W After reset 0 0 0 0 0 0 0 0E2H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...

Page 75: ...21 P20 Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 0D3H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P3 P37 P36 P35 P34 P33 P32 P31 P30 Read Write R W R W R W R W R W R W...

Page 76: ...slow mode In power down mode and green mode the watchdog timer stops Always_On Enable watchdog timer function The watchdog timer actives and not stop in power down mode and green mode In high noisy e...

Page 77: ...earing watchdog timer program is only at one part of the program This way is the best structure to enhance the watchdog timer function Example An operation of watchdog timer is as following To clear t...

Page 78: ...g timer Generate time out at specific time intervals based on the selected clock frequency Interrupt function T0 timer function supports interrupt function When T0 timer occurs overflow the T0IRQ acti...

Page 79: ...Clear T0IRQ by program is necessary in interrupt procedure T0 timer can works in normal mode slow mode and green mode In green mode T0 keeps counting set T0IRQ and wakes up system when T0 timer overf...

Page 80: ...ING REGISTER T0C is T0 8 bit counter When T0C overflow occurs the T0IRQ flag is set as 1 and cleared by program The T0C decides T0 interval time through below equation to calculate a correct value It...

Page 81: ...A Set T0C register for T0 Interval time MOV A value B0MOV T0C A Clear T0IRQ B0BCLR FT0IRQ Enable T0 timer and interrupt function B0BSET FT0IEN Enable T0 interrupt function B0BSET FT0ENB Enable T0 time...

Page 82: ...exibility to implement IR carry signal motor control and brightness adjuster The main purposes of the TC0 timer are as following 8 bit programmable up counting timer Generate time out at specific time...

Page 83: ...upt service routine after TC0 overflow occurrence Clear TC0IRQ by program is necessary in interrupt procedure TC0 timer can works in normal mode slow mode and green mode But in green mode TC0 keep cou...

Page 84: ...enable event counter function TC0rate 2 0 bits are useless Bit 6 4 TC0RATE 2 0 TC0 timer clock source select bits 000 Fcpu 128 001 Fcpu 64 010 Fcpu 32 011 Fcpu 16 100 Fcpu 8 101 Fcpu 4 110 Fcpu 2 111...

Page 85: ...value 256 TC0 interrupt interval time TC0 clock rate Example To calculation TC0C and TC0R value to obtain 10ms TC0 interval time TC0 clock source is Fcpu 16MHz 16 1MHz Select TC0RATE 000 Fcpu 128 TC0...

Page 86: ...set as 1 Reload TC0C from TC0R automatically TC0IRQ is cleared by program 0x01 0x02 0x03 0xFE 0xFF TC0R 8 3 8 PULSE WIDTH MODULATION PWM The PWM is duty cycle programmable design to offer various PWM...

Page 87: ...easily to implement carry signal on off operation not to control TC0ENB bit PWM Output PWM0OUT 1 The pin exchanges to output mode and outputs PWM signal automatically PWM0OUT 0 The pin exchanges to l...

Page 88: ...B0MOV TC0R A Clear TC0IRQ B0BCLR FTC0IRQ Enable TC0 timer and interrupt function B0BSET FTC0IEN Enable TC0 interrupt function B0BSET FTC0ENB Enable TC0 timer TC0 PWM CONFIGURATION Reset TC0 timer CLR...

Page 89: ...s resolution The capture timer builds in programmable trigger edge selection to decide the start stop trigger event 10 bit event counter The 10 bit event counter to detect event source for accumulativ...

Page 90: ...upt procedure T1 timer can works in normal mode slow mode and green mode 0x0000 or n by program Clock Source T1CH T1CL T1IRQ T1 timer overflows T1IRQ set as 1 Reload T1CH T1CL by program T1IRQ is clea...

Page 91: ...abling T1 timer 0A0H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T1M T1ENB T1rate2 T1rate1 T1rate0 T1CKS Read Write R W R W R W R W R W After reset 0 0 0 0 0 Bit 7 T1ENB T1 counter control bit 0 D...

Page 92: ...egisters The timer counter is double buffer design The core bus is 8 bit so access 16 bit data needs a latch flag to avoid the transient status affect the 16 bit data mistake occurrence Under write mo...

Page 93: ...ialization n 1 CPTStart 1 Rising Edge T1 starts to count T1 is counting Falling Edge T1 stops counting CPTStart 0 n is the high pulse width period Read it by program through T1CH T1CL registers The hi...

Page 94: ...eriod of a continuous input signal The measure is through T1 timer by trigger selection The event counter is controlled by CPTVC bit When CPTVC 0 the event counter is disabled When CPTVC 1 the event c...

Page 95: ...T1VCL1 T1VCL0 Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 0A4H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T1VCH T1VCH1 T1VCH0 Read Write R W R W After Reset 0 0 The T1...

Page 96: ...OR SINGLE CYCLE MEASUREMENT CONFIGURATION Reset T1 timer MOV A 0x00 Clear T1M register B0MOV T1M A Set T1 clock rate select input source and select enable T1 capture timer MOV A 0nnnm000b nnn is T1rat...

Page 97: ...t capture timer function B0MOV T1CKSM A CPTG 1 0 must be set as 01 High pulse width measurement Clear T1CH T1CL CLR T1CH Clear high byte first CLR T1CL Clear low byte Set T1VCH T1VCL 10 bit capture ti...

Page 98: ...istive sensor the RFC clock frequency is different T1 provides pulse width measurement and input frequency measurement functions to measure high low speed RFC clock RFC pin is shared with port 1 When...

Page 99: ...RC circuit until the voltage level higher than ViH of RFC cahnnel Then RFC channel exchanges to discharge operation until voltage level under ViL The charge discharge operation obtains the RFC oscill...

Page 100: ...e P1 0 GPIO function P1 1 P1 2 P1 3 P1 4 are GPIO mode 001 Select RFC1 channel Disable P1 1 GPIO function P1 0 P1 2 P1 3 P1 4 are GPIO mode 010 Select RFC2 channel Disable P1 2 GPIO function P1 0 P1 1...

Page 101: ...001000B Configure and enable T1 capture timer B0MOV T1CKSM A MOV A 0 Set T1 event counter buffers B0MOV T1VCH A MOV A 0xFF B0MOV T1VCL A B0BCLR FT1IRQ Clear T1 interrupt request flag Set RFC CLR P1UR...

Page 102: ...W After reset 0 0 0 0 0 0 0 0 Bit 7 6 CPCK 1 0 VLCD charge pump clock selection CPCK 1 0 Charge pump Clock 00 32KHz 01 16KHz 10 4KHz 11 1KHz Note In general speaking 1KHz charge pump clock is enough...

Page 103: ...uF 0 1uF 0 1uF Charge Pump Output Voltage 0 1uF VLCD Power Source Basic C type LCD Application Circuit LCD C type mode only supports 1 3 bias In C type mode connect a 0 1uF capacitor between C and C p...

Page 104: ...2 Bias Bias 1 VDD 1 2 VDD 1 2 VDD MCU VLCD V2 V1 VSS 100Kohm 100Kohm 100Kohm C C 1 3 bias 1 4 duty R type LCD Circuit VSS 0 1uF 0 1uF 0 1uF MCU VLCD V2 V1 VSS 100Kohm 100Kohm C C 1 2 bias 1 4 duty R t...

Page 105: ...0Ch 2 0Ch 3 0Dh SEG13 0Dh 0 0Dh 1 0Dh 2 0Dh 3 0Eh SEG14 0Eh 0 0Eh 1 0Eh 2 0Eh 3 0Fh SEG15 0Fh 0 0Fh 1 0Fh 2 0Fh 3 10h SEG16 10h 0 10h 1 10h 2 10h 3 1Bh SEG27 1Bh 0 1Bh 1 1Bh 2 1Bh 3 1Ch SEG28 1Ch 0 1...

Page 106: ...LCD VLCD VSS 1 2 VLCD VLCD VSS 1 2 VLCD VLCD VSS 1 2 VLCD VLCD VSS 1 2 VLCD ON OFF ON ON ON OFF OFF OFF VLCD VSS 1 2 VLCD ON ON ON ON OFF OFF OFF OFF VLCD VSS 1 3 VLCD 2 3 VLCD VLCD VSS 1 3 VLCD 2 3 V...

Page 107: ...1 N C OR A I A A or I 1 XOR A M A A xor M 1 XOR M A M A xor M 1 N XOR A I A A xor I 1 SWAP M A b3 b0 b7 b4 M b7 b4 b3 b0 1 P SWAPM M M b3 b0 b7 b4 M b7 b4 b3 b0 1 N R RRC M A RRC M 1 O RRCM M M RRC M...

Page 108: ...n Vss Vdd 3V 100 200 300 K Vin Vss Vdd 5V 50 100 150 I O output source current IoH Vop Vdd 0 5V 8 mA sink current IoL Vop Vss 0 5V 8 INTn trigger pulse width Tint0 INT0 interrupt request pulse width 2...

Page 109: ...TERISTIC GRAPHS The Graphs in this section are for design guidance not tested or guaranteed In some graphs the data presented are outside specified operating range This is for information only and dev...

Page 110: ...unctions must be through SN8P2318 real chip The real chip provides an EV KIT to achieve LCD and RFC functions emulations For SN8P2318 ICE emulation the EV Kit includes LCD RFC LVD2 4V 3 6V and switch...

Page 111: ...on SN8ICE2K Plus 2 power switch to start emulation 4 If the power indicator LED D1 doesn t light the EV kit occurs some mistakes Please contact SONIX s agent for maintain service 5 It is necessary to...

Page 112: ...DIP46 PGM OTPCLK 5 6 OE ShiftDat DIP 4 4 45 DIP45 D1 7 8 D0 DIP 5 5 44 DIP44 D3 9 10 D2 DIP 6 6 43 DIP43 D5 11 12 D4 DIP 7 7 42 DIP42 D7 13 14 D6 DIP 8 8 41 DIP41 VDD 15 16 VPP DIP 9 9 40 DIP40 HLS 1...

Page 113: ...SONiX TECHNOLOGY CO LTD Page 113 Version 1 5 14 2 SN8P2317 SN8P2318 OTP PROGRAMMING TOOL WR080 is writer board for SN8P2318 LQFP64 OTP programming socket connection MP125 is transition board for SN8P...

Page 114: ...ector IC and JP3 48 pin text tool Pin Assignment IC and JP1 20 pin text tool Pin Assignment JP1 JP2 Pin Number JP1 JP2 Pin Name IC Pin Number IC Pin Name JP3 Pin Number IC Pin Number IC Pin Name 1 VDD...

Page 115: ...er H Dice F LQFP Device 2317 2318 SN8 X PART No X X X P OTP 15 3 MARKING EXAMPLE Wafer Dice Name ROM Type Device Package Temperature Material S8P2318W OTP 2318 Wafer 20 85 SN8P2318H OTP 2318 Dice 20 8...

Page 116: ...ntroller SONiX TECHNOLOGY CO LTD Page 116 Version 1 5 15 4 DATECODE SYSTEM X X X X XXXXX Year Month 1 January 2 February 9 September A October B November C December SONiX Internal Use Day 1 01 2 02 9...

Page 117: ...0 050 1 400 0 150 A2 0 054 0 009 0 057 1 360 0 220 1 450 b 0 007 0 009 0 011 0 170 0 220 0 270 b1 0 007 0 009 0 170 0 230 C 0 004 0 008 0 090 0 200 C1 0 004 0 006 0 090 0 160 D 0 472 12 000 D1 0 394 1...

Page 118: ...16 2 LQFP 48 PIN SYMBOLS MIN NOR MAX MIN NOR MAX inch mm A 0 06 1 6 A1 0 00 0 01 0 05 0 15 A2 0 05 0 06 1 35 1 45 c1 0 00 0 01 0 09 0 16 D 0 35 BSC 9 00 BSC D1 0 27 BSC 7 00 BSC E 0 35 BSC 9 00 BSC E1...

Page 119: ...r death may occur Should Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subsidiaries affiliate...

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