SONIX SN8P2201 User Manual Download Page 109

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SN8P2200 Series

USB 1.1 Low-Speed 8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD

Page 109

Version 1.7

10.4

PS2_2 DESCRIPITON

PS2_2 interface is using P1.0, P1.1 open-drain mode to do PS/2 interface. The PS/2 pull-up resistors are external 5K
ohm by hardware design. Set P1.0, P1.1 to be open-drain structure by P1OC register and PS/2 communication is
controlled by firmware.

External hardware must include external 5K ohm pull-up resistors.

P1.0, P1.1 must be set as open-drain mode.

Use firmware to make PS/2 communication routine.

P10OC=1

P10M

Output

Latch

P11OC=1

P11M

Output

Latch

P1.0

P1.1

P1.0

P1.1

HOST
Terminal

VDD (5V)

5K
ohm

Summary of Contents for SN8P2201

Page 1: ...ned intended or authorized for us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which t...

Page 2: ...fy OTP program pin number of section 14 VER1 0 Nov 2006 1 Modify ELECTRICAL CHARACTERISTIC 2 Modify USB register naming 3 Modify code option IHRC description 4 Modify P0UR register VER1 1 Jan 2007 1 M...

Page 3: ...E DESCRIPTION 19 2 1 1 4 JUMP TABLE DESCRIPTION 21 2 1 1 5 CHECKSUM CALCULATION 23 2 1 2 CODE OPTION TABLE 24 2 1 3 DATA MEMORY RAM 25 2 1 4 SYSTEM REGISTER 26 2 1 4 1 SYSTEM REGISTER TABLE 26 2 1 4 2...

Page 4: ...Bias Reset Circuit 48 3 6 5 External Reset IC 48 4 SYSTEM CLOCK 49 4 1 OVERVIEW 49 4 2 CLOCK BLOCK DIAGRAM 49 4 3 OSCM REGISTER 50 4 4 SYSTEM HIGH CLOCK 51 4 4 1 INTERNAL HIGH RC 51 4 4 2 EXTERNAL HIG...

Page 5: ...3 T0C COUNTING REGISTER 78 8 2 4 T0 TIMER OPERATION SEQUENCE 79 8 3 TIMER COUNTER 0 TC0 80 8 3 1 OVERVIEW 80 8 3 2 TC0M MODE REGISTER 81 8 3 3 TC0C COUNTING REGISTER 82 8 3 4 TC0R AUTO LOAD REGISTER...

Page 6: ...REGISTER 105 9 5 8 USB DATA POINTER 1 REGISTER 105 9 5 9 USB DATA REGISTER 105 9 5 10 USB STATUS REGISTER 105 9 5 11 UPID REGISTER 106 10 PS 2 INTERFACE 107 10 1 OVERVIEW 107 10 2 PS 2 OPERATION 107...

Page 7: ...14 PIN 123 15 5 SOP 28 PIN 124 15 6 SOP 24 PIN 125 15 7 SOP 20 PIN 126 15 8 SOP 18 PIN 127 15 9 SOP 14 PIN 128 15 10 SSOP 28 PIN 129 15 11 SSOP 24 PIN 130 15 12 SSOP 20 PIN 131 15 13 SSOP 16 PIN 132 1...

Page 8: ...P1 P5 Open drain P1 0 P1 1 One channel PWM output PWM External interrupt P0 0 controlled by PEDGE One channel Buzzer output BZ0 Timer capture input pin P0 1 P0 2 controlled Two 8 bit timer counters T...

Page 9: ...SYSTEM BLOCK DIAGRAM INTERRUPT CONTROL EXTERNAL HIGH OSC ACC INTERNAL LOW RC INTERNAL 6M RC TIMING GENERATOR RAM SYSTEM REGISTERS LVD WATCHDOG TIMER TIMER COUNTER P0 P5 P1 PWM 0 BUZZER 0 ALU PC FLAGS...

Page 10: ...P0 2 T2IN 8 21 P5 7 P0 1 T1IN 9 20 P0 6 P0 0 INT0 10 19 P0 5 VSS 11 18 D SCLK P1 4 RST VPP 12 17 D SDATA VREG 13 16 VDD P1 3 XIN 14 15 P1 2 XOUT SN8P2204K SN8P2204S SN8P2204X SN8P2203K SK DIP 24 pins...

Page 11: ...12 D SDATA VREG 8 11 VDD P1 3 XIN 9 10 P1 2 XOUT SN8P2202P SN8P2202S NC 1 U 20 NC P1 0 2 19 P5 4 BZ0 PWM0 P1 1 3 18 P5 3 P0 2 T2IN 4 17 P5 2 P0 1 T1IN 5 16 P5 1 P0 0 INT0 6 15 P5 0 VSS 7 14 D SCLK P1...

Page 12: ...INT0 3 12 P5 0 VSS 4 11 D SCLK P1 4 RST VPP 5 10 D SDATA VREG 6 9 VDD P1 3 XIN 7 8 P1 2 XOUT SN8P2201P SN8P2201S NC 1 U 16 NC P1 0 2 15 P5 4 BZ0 PWM0 P1 1 3 14 P5 1 P0 0 INT0 4 13 P5 0 VSS 5 12 D SCL...

Page 13: ...enable P1 2 Port 1 2 bi direction pin under internal 16M RC and external RC Schmitt trigger structure and built in pull up resisters as input mode Built wakeup function P1 3 XIN I O XIN Oscillator inp...

Page 14: ...cture Pull Up Pin Output Latch PnM PnUR Input Bus PnM Output Bus Port 1 0 Port 1 1 structure Pull Up Pin Output Latch PnM PnUR Input Bus PnM Output Bus P1OC Open Drain Port 1 2 1 3 structure Oscillato...

Page 15: ...UNIT CPU 2 1 MEMORY MAP 2 1 1 PROGRAM MEMORY ROM 6K words ROM ROM 0000H Reset vector User reset vector Jump to user start address 0001H 0007H General purpose area 0008H Interrupt vector User interrup...

Page 16: ...on reset external reset or watchdog timer overflow reset then the chip will restart the program from address 0000h and all system registers will be set as default values It is easy to know reset statu...

Page 17: ...or The following example shows the way to define the interrupt vector in the program memory Note PUSH POP instructions save and load ACC PFLAG without NT0 NPD PUSH POP buffer is a unique buffer and on...

Page 18: ...f user program User program JMP START End of user program MY_IRQ The head of interrupt service routine PUSH Save ACC and PFLAG register to buffers POP Load ACC and PFLAG register from buffers RETI End...

Page 19: ...ABLE1 L To set lookup table1 s low address MOVC To lookup data R 00H ACC 35H Increment the index address for next address INCMS Z Z 1 JMP F Z is not overflow INCMS Y Z overflow FFH 00 Y Y 1 NOP MOVC T...

Page 20: ...o define a word 16 bits data DW 5105H DW 2012H The other example of loop up table is to add Y or Z index register by accumulator Please be careful if carry happen Example Increase Y and Z register by...

Page 21: ...ry after PCL ACC PCH adds one automatically If PCL borrow after PCL ACC PCH keeps value and not change Example Jump table ORG 0X0100 The jump table is from the head of the ROM boundary B0ADD PCL A PCL...

Page 22: ...le routine begin from next RAM boundary 0x0100 Example JMP_A operation Before compiling program ROM address B0MOV A BUF0 BUF0 is from 0 to 4 JMP_A 5 The number of the jump table listing is five 0X00FD...

Page 23: ...d address to end_addr2 CLR Y Set Y to 00H CLR Z Set Z to 00H MOVC B0BSET FC Clear C flag ADD DATA1 A Add A to Data1 MOV A R ADC DATA2 A Add R to Data2 JMP END_CHECK Check if the YZ address the end of...

Page 24: ...ways_On Watchdog timer is always on enable even in power down and green mode Enable Enable watchdog timer Watchdog timer stops in power down mode and green mode Watch_Dog Disable Disable Watchdog func...

Page 25: ...Y CO LTD Page 25 Version 1 7 2 1 3 DATA MEMORY RAM 256 X 8 bit RAM Address RAM location 000h 07Fh General purpose area BANK 0 080h System register BANK 0 0FFh End of bank 0 area 80h FFh of Bank 0 stor...

Page 26: ...UE3R Endpoint 0 3 control registers UDP0 USB FiFo 0 address pointer UDR0 USB FiFo 0 data buffer by UDP0 point to UDP1 USB FiFo 1 address pointer UDR1 USB FiFo 1 data buffer by UDP1 point to USTATUS US...

Page 27: ...T2IEN T1IEN P00IEN R W INTEN 0CAH CPUM1 CPUM0 CLKMD STPHX R W OSCM 0CCH WDTR7 WDTR6 WDTR5 WDTR4 WDTR3 WDTR2 WDTR1 WDTR0 W WDTR 0CDH TC0R7 TC0R6 TC0R5 TC0R4 TC0R3 TC0R2 TC0R1 TC0R0 W TC0R 0CEH PC7 PC6...

Page 28: ...ut all the 0 and 1 as it indicates in the above table 2 All of register names had been declared in SN8ASM assembler 3 One bit name had been declared in SN8ASM assembler with F prefix code 4 b0bset b0b...

Page 29: ...t be access by B0MOV instruction during the instant addressing mode Example Read and write ACC value Read ACC data and store in BUF data memory MOV BUF A Write a immediate data into ACC MOV A 0FH Wri...

Page 30: ...lag NT0 NPD Reset Status 0 0 Watch dog time out 0 1 Reserved 1 0 Reset by LVD 1 1 Reset by external Reset Pin Bit 2 C Carry flag 1 Addition with carry subtraction without borrowing rotation with shift...

Page 31: ...it 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PC PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 After reset 0 0 0 0 0 0 0 0 0 0 0 0 0 PCH PCL ONE ADDRESS SKIPPING There are...

Page 32: ...CS BUF0 JMP C0STEP Jump to C0STEP if ACC is not zero C0STEP NOP INCMS instruction INCMS BUF0 JMP C0STEP Jump to C0STEP if BUF0 is not zero C0STEP NOP If the destination decreased by 1 which results un...

Page 33: ...lue by the three instructions and don t care PCL overflow problem Note PCH only support PC up counting result and doesn t support PC down counting When PCL is carry after PCL ACC PCH adds one automati...

Page 34: ...R W R W R W After reset 083H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Z ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0 Read Write R W R W R W R W R W R W R W R W After reset Example Uses Y Z...

Page 35: ...r store high byte data of look up table MOVC instruction executed the high byte data of specified ROM address will be stored in R register and the low byte data will be stored in ACC 082H Bit 7 Bit 6...

Page 36: ...7 working register 2 2 2 DIRECTLY ADDRESSING MODE The directly addressing mode moves the content of RAM location in or out of ACC Example Move 0x12 RAM location data into ACC B0MOV A 12H To get a cont...

Page 37: ...instruction are executed The STKP register is a pointer designed to point active level in order to push or pop up data from stack buffer The STKnH and STKnL are the stack buffers to store program coun...

Page 38: ...service routine Stack operation is a LIFO type Last in and first out The stack pointer STKP and stack buffer STKnH and STKnL are located in the system register area bank 0 0DFH Bit 7 Bit 6 Bit 5 Bit 4...

Page 39: ...STK1L 3 1 0 0 STK2H STK2L 4 0 1 1 STK3H STK3L 5 0 1 0 STK4H STK4L 6 0 0 1 STK5H STK5L 7 0 0 0 STK6H STK6L 8 1 1 1 STK7H STK7L 8 1 1 0 Stack Over error There are Stack Restore operations correspond to...

Page 40: ...s cleared After reset status released the system boots up and program starts to execute from ORG 0 The NT0 NPD flags indicate system reset status The system can depend on NT0 NPD status and go to diff...

Page 41: ...llator is not fixed RC type oscillator s start up time is very short but the crystal type is longer Under client terminal application users have to take care the power on reset time for the master ter...

Page 42: ...tchdog timer by program Under error condition system is in unknown situation and watchdog can t be clear by program before watchdog timer overflow Watchdog timer overflow occurs and the system is rese...

Page 43: ...and V1 doesn t touch the below area and not effect the system operation But the V2 and V3 is under the below area and may induce the system error occurrence Let system under dead band includes some co...

Page 44: ...The electrical characteristic section shows the system voltage to executing rate relationship Vdd V System Rate Fcpu System Mini Operating Voltage System Reset Voltage Dead Band Area Normal Operating...

Page 45: ...re detail LVD information is in the electrical characteristic section Watchdog reset The watchdog timer is a protection to make sure the system executes well Normally the watchdog timer would be clear...

Page 46: ...evel the system keeps reset status and waits external reset pin released z System initialization All system registers is set as initial conditions and system is ready z Oscillator warm up Oscillator o...

Page 47: ...circuit and Diode RC reset circuit is necessary to limit any current flowing into reset pin from external capacitor C in the event of reset pin breakdown due to Electrostatic Discharge ESD or Electri...

Page 48: ...If the VDD drops and the voltage lower than reset pin detect level the system would be reset If want to make the reset active earlier set the R2 R1 and the cap between VDD and C terminal voltage is la...

Page 49: ...16KHz 3V 32KHz 5V Both the high speed clock and the low speed clock can be system clock Fosc The system clock in slow mode is divided by 4 to be the instruction cycle Fcpu Normal Mode High Clock Fcpu...

Page 50: ...cillator free run stop Internal low speed RC oscillator is still running Bit 2 CLKMD System high Low clock mode control bit 0 Normal dual mode System clock is high clock 1 Slow mode System clock is in...

Page 51: ...purpose I O pins In IHRC_RTC mode the system clock is from internal 6MHz RC type oscillator and XIN XOUT pins are connected with external 32768 crystal for real time clock RTC z IHRC High clock is int...

Page 52: ...00 25 00 30 00 35 00 40 00 45 00 2 1 2 5 3 3 1 3 3 3 5 4 4 5 5 5 5 6 6 5 7 VDD V Freq KHz ILRC The internal low RC supports watchdog clock source and system slow mode controlled by CLKMD Flosc Intern...

Page 53: ...struction cycle Fcpu This way is useful in RC mode Example Fcpu instruction cycle of external oscillator B0BSET P0M 0 Set P0 0 to be output mode for outputting Fcpu toggle signal B0BSET P0 0 Output Fc...

Page 54: ...ode description MODE NORMAL SLOW GREEN POWER DOWN SLEEP REMARK EHOSC Running By STPHX By STPHX Stop IHRC Running By STPHX By STPHX Stop ILRC Running Running Running Stop EHOSC with RTC Running By STPH...

Page 55: ...eed oscillator is still running B0BCLR FCLKMD To set CLKMD 0 Example Switch slow mode to normal mode The external high speed oscillator stops If external high clock stop and program want to switch bac...

Page 56: ...B0BCLR FT0IEN To disable T0 interrupt service B0BCLR FT0IRQ To clear T0 interrupt request B0BSET FT0ENB To enable T0 timer Go into green mode B0BCLR FCPUM0 To set CPUMx 10 B0BSET FCPUM1 Note During t...

Page 57: ...MCU waits for 4 internal 6MHz clock or 2048 external 6MHz clocks as the wakeup time to stable the oscillator circuit After the wakeup time the system goes into the normal mode Note Wakeup from green m...

Page 58: ...e is executed the GIE bit in STKP register will clear to 0 for stopping other interrupt request On the contrast when interrupt service exits the GIE bit will set to 1 to accept the next interrupts req...

Page 59: ...it 4 Bit 3 Bit 2 Bit 1 Bit 0 INTEN USBIEN TC0IEN T0IEN T2IEN T1IEN P00IEN Read Write R W R W R W R W R W R W After reset 0 0 0 0 0 0 Bit 0 P00IEN External P0 0 interrupt INT0 control bit 0 Disable INT...

Page 60: ...one T1 interrupt request 1 T1 interrupt request Bit 2 T2IRQ T2 timer interrupt request flag 0 None T2 interrupt request 1 T2 interrupt request Bit 4 T0IRQ T0 timer interrupt request flag 0 None T0 int...

Page 61: ...o instruction save and load ACC PFLAG data into buffers and avoid main routine error after interrupt service routine finishing Note PUSH POP instructions save and load ACC PFLAG without NT0 NPD PUSH P...

Page 62: ...direction the INT0 interrupt request flag INT0IRQ is latched while system wake up from power down mode or green mode by P0 0 wake up trigger System inserts to interrupt vector ORG 8 after wake up imme...

Page 63: ...ervice routine ORG 8 Interrupt vector JMP INT_SERVICE INT_SERVICE Push routine to save ACC and PFLAG to buffers B0BTS1 FP00IRQ Check P00IRQ JMP EXIT_INT P00IRQ 0 exit interrupt vector B0BCLR FP00IRQ R...

Page 64: ...errupt request setup B0BCLR FT0IEN Disable T0 interrupt service B0BCLR FT0ENB Disable T0 timer MOV A 20H B0MOV T0M A Set T0 clock Fcpu 64 MOV A 74H Set T0C initial value 74H B0MOV T0C A Set T0 interva...

Page 65: ...uation Example TC0 interrupt request setup B0BCLR FTC0IEN Disable TC0 interrupt service B0BCLR FTC0ENB Disable TC0 timer MOV A 20H B0MOV TC0M A Set TC0 clock Fcpu 64 MOV A 74H Set TC0C initial value 7...

Page 66: ...be cautious with the operation under multi interrupt situation Example USB interrupt request setup B0BCLR FUSBIEN Disable USB interrupt service B0BCLR FUSBENB Disable USB timer B0BCLR FUSBIRQ Clear US...

Page 67: ...tion under multi interrupt situation Example T1 interrupt request setup B0BCLR FT1IEN Disable T1 interrupt service B0BCLR FT1ENB Disable T1 timer MOV A 20H B0MOV T1M A Set T1 clock Fcpu 64 and falling...

Page 68: ...tion under multi interrupt situation Example T2 interrupt request setup B0BCLR FT2IEN Disable T2 interrupt service B0BCLR FT2ENB Disable T2 timer MOV A 20H B0MOV T2M A Set T2 clock Fcpu 64 and falling...

Page 69: ...t flag in interrupt routine Example Check the interrupt request under multi interrupt operation ORG 8 Interrupt vector JMP INT_SERVICE INT_SERVICE Push routine to save ACC and PFLAG to buffers INTP00C...

Page 70: ...Write R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0C5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5M P57M P56M P55M P54M P53M P52M P51M P50M Read Write R W R W R W R W R W R W R W R W...

Page 71: ...et 0 0 0 0 0 0 0 0E5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5UR P57R P56R P55R P54R P53R P52R P51R P50R Read Write W W W W W W W W After reset 0 0 0 0 0 0 0 0 Note P1 4 is an input only pin...

Page 72: ...n be 2nd PS 2 interface on chip More detail information refer to PS 2 chapter 0E9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1OC P11OC P10OC Read Write W W After reset 0 0 Bit 1 0 P1nOC Port 1...

Page 73: ...0 0 0 0 0 0 0 0D5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5 P57 P56 P55 P54 P53 P52 P51 P50 Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Note The P14 keeps 1 when...

Page 74: ...ow Speed oscillator sec VDD Internal Low RC Freq Watchdog Overflow Time 3V 16KHz 512ms 5V 32KHz 256ms Note If watchdog is Always_On mode it keeps running event under power down mode or green mode Watc...

Page 75: ...ing watchdog timer program is only at one part of the program This way is the best structure to enhance the watchdog timer function Example An operation of watchdog timer is as following To clear the...

Page 76: ...t programmable up counting timer Generates interrupts at specific time intervals based on the selected clock frequency RTC timer Generates interrupts at real time intervals based on the selected clock...

Page 77: ...ate0 T0TB Read Write R W R W R W R W R W After reset 0 0 0 0 0 Bit 0 T0TB RTC clock source control bit 0 Disable RTC T0 clock source from Fcpu 1 Enable RTC Bit 6 4 T0RATE 2 0 T0 internal clock select...

Page 78: ...set 1ms interval time for T0 interrupt High clock is internal 6MHz Fcpu Fosc 1 Select T0RATE 010 Fcpu 64 T0C initial value 256 T0 interrupt interval time input clock 256 1ms 6MHz 1 64 256 10 3 6 106...

Page 79: ...t function is disabled B0BCLR FT0IRQ T0 interrupt request flag is cleared Set T0 timer rate MOV A 0xxx0000b The T0 rate control bits exist in bit4 bit6 of T0M The value is from x000xxxxb x111xxxxb B0M...

Page 80: ...pt to request interrupt service TC0 overflow time is 0xFF to 0X00 normally Under PWM mode TC0 overflow is decided by PWM cycle controlled by ALOAD0 and TC0OUT bits The main purposes of the TC0 timer i...

Page 81: ...output control bit Only valid when PWM0OUT 0 0 Disable P5 4 is I O function 1 Enable P5 4 is output TC0OUT signal Bit 2 ALOAD0 Auto reload control bit Only valid when PWM0OUT 0 0 Disable TC0 auto relo...

Page 82: ...56 0x00 0xFF 00000000b 11111111b Overflow per 256 count 1 0 0 256 0x00 0xFF 00000000b 11111111b Overflow per 256 count 1 0 1 64 0x00 0x3F xx000000b xx111111b Overflow per 64 count 1 1 0 32 0x00 0x1F x...

Page 83: ...2 TC0R1 TC0R0 Read Write W W W W W W W W After reset 0 0 0 0 0 0 0 0 The equation of TC0R initial value is as following TC0R initial value N TC0 interrupt interval time input clock N is TC0 overflow b...

Page 84: ...requency waveform is as following 1 2 3 4 1 2 3 4 TC0 Overflow Clock TC0OUT Buzzer Output Clock Example Setup TC0OUT output from TC0 to TC0OUT P5 4 The external high speed clock is 4MHz The TC0OUT fre...

Page 85: ...ource or B0BSET FTC0CKS Select TC0 external clock source Set TC0 timer auto load mode B0BCLR FALOAD0 Enable TC0 auto reload function or B0BSET FALOAD0 Disable TC0 auto reload function Set TC0 interrup...

Page 86: ...erence register with 00H Under PWM operating to change the PWM s duty cycle is to modify the TC0R Note TC0 is double buffer design Modifying TC0R to change PWM duty by program there is no glitch and e...

Page 87: ...d on PWM duty range From following diagram the TC0IRQ frequency is related with PWM duty TC0 Overflow TC0IRQ 1 PWM0 Output Duty Range 0 15 0xFF TC0C Value 0x00 PWM0 Output Duty Range 0 31 0xFF TC0C Va...

Page 88: ...R In every TC0C overflow PWM output High when TC0C TC0R PWM output Low If TC0R is changing in the program processing the PWM waveform will became as following diagram 1 1st PWM 2 Update PWM Duty 3 2nd...

Page 89: ...B B0MOV TC0M A Set the TC0 rate to Fcpu 4 MOV A 30 Set the PWM duty to 30 256 B0MOV TC0C A B0MOV TC0R A B0BCLR FTC0OUT Set duty range as 0 256 255 256 B0BCLR FALOAD0 B0BSET FPWM0OUT Enable PWM0 output...

Page 90: ...capture input mode has wake up function from power down mode and green mode Note T2 operation is equal to T1 operation Use Tn to mean T1 and T2 in follow sections The main purposes of the Tn 8 bit tim...

Page 91: ...cpu 256 001 fcpu 128 110 fcpu 4 111 fcpu 2 Bit 1 0 TnG1 0 Tn timer capture trigger selection 00 Falling edge trigger for period measurement 01 Rising edge trigger for period measurement 10 Rising edge...

Page 92: ...lication Program Clear TnC and TnIRQ Before using Tn timer capture have to know input signal information eg pulse width or period range to decide Tn time base The time base value selection has to avoi...

Page 93: ...se The combination of high and low pulses is a full cycle signal Rising to rising edge is the same Set Tn time base and select Tn edge as falling edge or rising edge the Tn function is to measure inpu...

Page 94: ...ar T1C B0BCLR FT1IRQ Clear T1IRQ JMP Chk_T1IRQ Measure next signal The T1C 75 Time base is 1 33us in T1RATE 101 Fcpu 8 and Fcpu 6MHz Input frequency 1 1 33us 75 10 025KHz 10KHz Above example is using...

Page 95: ...stop Tn counting TnG1 0 11 is negative pulse width measurement Falling edge starts Tn timer and rising edge stop Tn counting End of pulse width measurement TnIRQ 1 and cleared by firmware for next pul...

Page 96: ...LR T1C Clear T1C B0BCLR FT1IRQ Clear T1IRQ JMP Chk_T1IRQ Measure next signal The T1C 90 Time base is 1 33us in T1RATE 101 Fcpu 8 and Fcpu 6MHz Positive pulse width 1 33us 90 119 7 us 120 us Above exam...

Page 97: ...hardware handles the following USB bus activity independently of the microcontroller The USB machine will do Translate the encoded received data and format the data to be transmitted on the bus CRC ch...

Page 98: ...the error of reading or writing the endpoint FIFOs and to do the right USB request routine according to the flag Example Save the UDP0 UDP1 ACC and Status flag when interrupt request occurs To avoid t...

Page 99: ...rmware responds by sending its Device descriptor over the USB bus 9 The host generates control reads from the device to request the Configuration and Report descriptors 10 Once the device receives a S...

Page 100: ...it 4 UE0DI Indicate endpoint 0 data ready to host IN token 0 Data is ready in EP0 FIFO for USB host drawing out Firmware set the bit zero to indicate that data is ready Hardware will send an ACK to co...

Page 101: ...ware will send NAK handshakes response to any IN token sent to this endpoint In addition set this bit and the bit 4 of UPID register will send the STALL handshake response to any IN token sent to this...

Page 102: ...IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint 2 FIFO Bit 4 UE2DI Indicate endpoint 2 data ready to host IN token 0 Data is ready in...

Page 103: ...IN token sent to this endpoint Bit 5 UE3DO Indicate endpoint 3 data ready from host OUT token 0 Data doesn t finish carrying Data doesn t finish carrying Clear the bit by firmware after the FIFO data...

Page 104: ...A JMP user_define_routine read_endpoint0_FIFO_UDR1 MOV A UDR1 move FIFO s data to A JMP user_define_routine Example 3 Set endpoint 1 s FIFO address when writing data to FIFO EP1_FIFO_WRITE_Address B0B...

Page 105: ...E register 0xA4H to select the right FIFO 9 5 9 USB DATA REGISTER Store the data which UDP1 point to 0A8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UDR1 UDR17 UDR16 UDR15 UDR14 UDR13 UDR12 UDR11...

Page 106: ...ll send the STALL handshake response to any IN token sent to endpoint 0 0 Disable endpoint 0 STALL handshake response Bit 4 EP1STALL Send STALL handshakes to any IN token response sent to endpoint 1 1...

Page 107: ...ATA START BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 PARITY STOP LSB MSB One pocket includes start bit Clock and data pins are low status one byte data LSB to MSB parity bit odd parity and stop b...

Page 108: ...B 1 internal pull up resistor enable PS 2 communication is controlled by firmware PS2ENB VDD 5V SCKM 5K ohm Output Latch SCK SCK HOST Terminal PS2ENB VDD 5V SDAM 5K ohm Output Latch SDA SDA PS2M initi...

Page 109: ...s are external 5K ohm by hardware design Set P1 0 P1 1 to be open drain structure by P1OC register and PS 2 communication is controlled by firmware z External hardware must include external 5K ohm pul...

Page 110: ...R A M A A xor M 1 XOR M A M A xor M 1 N XOR A I A A xor I 1 SWAP M A b3 b0 b7 b4 M b7 b4 b3 b0 1 P SWAPM M M b3 b0 b7 b4 M b7 b4 b3 b0 1 N R RRC M A RRC M 1 O RRCM M M RRC M 1 N C RLC M A RLC M 1 E RL...

Page 111: ...EV kit SN8P2200 EV kit Rev A z IDE SONiX IDE M2IDE 1 08 This is brief version z Firmware Library USB_library_ver093 Detail information refer to SN8 MCU USB library doc document 12 1 ICE In Circuit Em...

Page 112: ...to SN8ICE2K USB includes three parts z Remove U20 and R15 devices z Modify U20 circuit Link pin2 pin13 pin3 pin5 pin6 pin9 and pin10 pin12 four lines z Modify Y2 crystal from 4MHz to 6MHz Original Mod...

Page 113: ...3 3V power supply Use LM3940 3 3V regulator to supply 3 3V power for PHY IC The outline of SN8P2200 EV kit is as following z CON1 CON2 ICE interface connected to SN8ICE2K USB z U1 U2 Level shift devi...

Page 114: ...P5 0 P5 5 JP8 VDD33V 1 2 3 U U5 SN8P2201P S 1 2 3 11 10 9 8 7 6 5 4 13 12 14 P1 0 P1 1 P0 0 INT0 D SCK D SDA VDD P1 2 XOUT P1 3 XIN VREG P1 4 RST VPP VSS P5 1 P5 0 P5 4 BZ0 PWM0 300MIL DIP DPDO1 VSS...

Page 115: ...must be connected z PS2_2 is from P1 0 and P1 1 in open drain mode The pull up resistor is external set SN8P2200 EV kit builds PS2_2 pull up resistor on board and controlled by S1 switch S1 ON PS2_2...

Page 116: ...16 Version 1 7 12 4 IDE Integrated Development Environment The IDE for SN8P2200 development and emulation is base on Sonix M2IDE to add USB FiFo window The user interface and operation method is equal...

Page 117: ...Vin Vdd 2 uA Vin Vss Vdd 3V 100 200 300 I O port pull up resistor Rup Vin Vss Vdd 5V 50 100 150 K PS 2 pull up resistor Pup Vin Vss Vdd 3 3V 2 5 5 8 K I O port input leakage current Ilekg Pull up res...

Page 118: ...OTPCLK DIP3 3 46 DIP46 D0 8 7 D1 DIP4 4 45 DIP45 D2 10 9 D3 DIP5 5 44 DIP44 D4 12 11 D5 DIP6 6 43 DIP43 D6 14 13 D7 DIP7 7 42 DIP42 VPP 16 15 VDD DIP8 8 41 DIP41 RST 18 17 HLS DIP9 9 40 DIP40 ALSB PDB...

Page 119: ...P5 1 21 P5 1 15 P5 1 16 P5 1 7 D1 8 D0 9 D3 10 D2 11 D5 12 D4 13 D7 14 D6 15 VDD 16 VPP 12 RST 10 RST 7 RST 8 RST 17 HLS 18 RST 19 20 ALSB PDB 2 P1 1 2 P1 1 2 P1 1 3 P1 1 Programming Information of SN...

Page 120: ...ATION z 15 1 SK DIP 28 PIN MIN NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 210 5 334 A1 0 015 0 381 A2 0 114 0 130 0 135 2 896 3 302 3 429 D 1 390 1 390 1 400 35 306 35 306 35 560 E 0 310 7 874 E1 0 283 0...

Page 121: ...K DIP 24 PIN MIN NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 210 5 334 A1 0 015 0 381 A2 0 125 0 130 0 135 3 175 3 302 3 429 D 1 230 1 250 1 280 31 242 31 75 32 51 E 0 300 BSC 7 62 BSC E1 0 252 0 258 0 26...

Page 122: ...P DIP 18 PIN MIN NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 210 5 334 A1 0 015 0 381 A2 0 125 0 130 0 135 3 175 3 302 3 429 D 0 880 0 900 0 920 22 352 22 860 23 368 E 0 300 7 620 E1 0 245 0 250 0 255 6...

Page 123: ...4 P DIP 14 PIN MIN NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 210 5 334 A1 0 015 0 381 A2 0 125 0 130 0 135 3 175 3 302 3 429 D 0 735 0 075 0 775 18 669 1 905 19 685 E 0 300 7 62 E1 0 245 0 250 0 255 6...

Page 124: ...15 5 SOP 28 PIN MIN NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 093 0 099 0 104 2 362 2 502 2 642 A1 0 004 0 008 0 012 0 102 0 203 0 305 D 0 697 0 705 0 713 17 704 17 907 18 110 E 0 291 0 295 0 299 7 391...

Page 125: ...LTD Page 125 Version 1 7 15 6 SOP 24 PIN MIN NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 104 2 642 A1 0 004 0 102 D 0 599 0 600 0 624 15 214 15 24 15 84 E 0 291 0 295 0 299 7 391 7 493 7 595 H 0 394 0 407...

Page 126: ...15 7 SOP 20 PIN MIN NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 093 0 099 0 104 2 362 2 502 2 642 A1 0 004 0 008 0 012 0 102 0 203 0 305 D 0 496 0 502 0 508 12 598 12 751 12 903 E 0 291 0 295 0 299 7 391...

Page 127: ...15 8 SOP 18 PIN MIN NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 093 0 099 0 104 2 362 2 502 2 642 A1 0 004 0 008 0 012 0 102 0 203 0 305 D 0 447 0 455 0 463 11 354 11 557 11 760 E 0 291 0 295 0 299 7 391...

Page 128: ...MBOLS inch mm A 0 058 0 064 0 068 1 4732 1 6256 1 7272 A1 0 004 0 010 0 1016 0 254 B 0 013 0 016 0 020 0 3302 0 4064 0 508 C 0 0075 0 008 0 0098 0 1905 0 2032 0 2490 D 0 336 0 341 0 344 8 5344 8 6614...

Page 129: ...NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 08 2 13 A1 0 00 0 01 0 05 0 25 A2 0 06 0 07 0 07 1 63 1 75 1 88 b 0 01 0 01 0 22 0 38 C 0 00 0 01 0 09 0 20 D 0 39 0 40 0 41 9 90 10 20 10 50 E 0 29 0 31 0 32...

Page 130: ...m A 0 053 0 064 0 069 1 346 1 625 1 752 A1 0 004 0 006 0 010 0 101 0 152 0 254 A2 0 059 1 499 D 0 337 0 341 0 344 8 559 8 661 8 737 E 0 228 0 236 0 244 5 791 5 994 6 197 E1 0 150 0 154 0 157 3 81 3 91...

Page 131: ...04 0 006 0 010 0 100 0 150 0 250 A2 0 059 1 500 b 0 008 0 010 0 012 0 200 0 254 0 300 c 0 007 0 008 0 010 0 180 0 203 0 250 D 0 337 0 341 0 344 8 560 8 660 8 740 E 0 228 0 236 0 244 5 800 6 000 6 200...

Page 132: ...SYMBOLS inch mm A 0 053 0 069 1 3462 1 7526 A1 0 004 0 010 0 1016 0 254 A2 0 059 1 4986 b 0 008 0 012 0 2032 0 3048 b1 0 008 0 011 0 2032 0 2794 c 0 007 0 010 0 1778 0 254 c1 0 007 0 009 0 1778 0 2286...

Page 133: ...SN8P2200 Series USB 1 1 Low Speed 8 Bit Micro Controller SONiX TECHNOLOGY CO LTD Page 133 Version 1 7 15 14 QFN 16 PIN...

Page 134: ...ne This note listed the production definition of all 8 bit MCU for order or obtain information This definition is only for Blank OTP MCU 16 2 MARKING INDETIFICATION SYSTEM Title SONiX 8 bit MCU Produc...

Page 135: ...70 PB Free Package SN8P2204XB OTP 2204 SSOP 0 70 PB Free Package SN8P2204PG OTP 2204 P DIP 0 70 Green Package SN8P2204SG OTP 2204 SOP 0 70 Green Package SN8P2204XG OTP 2204 SSOP 0 70 Green Package SN8...

Page 136: ...ur Should Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subsidiaries affiliates and distribut...

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