SN8P1829
8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Reg 128 dots LCD driver
SONiX TECHNOLOGY CO., LTD
Page 81
Version 1.0
INTEN INTERRUPT ENABLE REGISTER
INTEN is the interrupt request control register including four internal interrupts, three external interrupts and SIO
interrupt enable control bits. One of the register to be set “1” is to enable the interrupt request function. Once of the
interrupt occur, the program jump to ORG 8 to execute interrupt service routines. The program exits the interrupt
service routine when the returning interrupt service routine instruction (RETI) is executed.
INTEN initial value = x000 0000
0C9H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTEN
0 TC1IEN
TC0IEN
T0IEN
SIOIEN 0 P01IEN
P00IEN
- R/W R/W R/W R/W - R/W
R/W
P00IEN
: External P0.0 interrupt control bit. 0 = disable, 1 = enable.
P01IEN :
External P0.1 interrupt control bit. 0 = disable, 1 = enable.
SIOIEN :
SIO interrupt control bit. 0 = disable, 1 = enable.
T0IEN :
T0 timer interrupt control bit. 0 = disable, 1 = enable.
TC0IEN :
Timer 0 interrupt control bit. 0 = disable, 1 = enable.
TC1IEN :
Timer 1 interrupt control bit. 0 = disable, 1 = enable.
INTRQ INTERRUPT REQUEST REGISTER
INTRQ is the interrupt request flag register. The register includes all interrupt request indication flags. Each one of
these interrupt request occurs, the bit of the INTRQ register would be set “1”. The INTRQ value needs to be clear by
programming after detecting the flag. In the interrupt vector of program, users know the any interrupt requests
occurring by the register and do the routine corresponding of the interrupt request.
INTRQ initial value = x000 0000
0C8H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTRQ
0 TC1IRQ
TC0IRQ
T0IRQ
SIOIRQ 0 P01IRQ
P00IRQ
- R/W R/W R/W R/W - R/W
R/W
Bit0
P00IRQ:
External P0.0 interrupt request bit.
0 = non-request
1 = request.
Bit1
P01IRQ:
External P0.1 interrupt request bit.
0 = non-request
1 = request.
Bit3
SIOIRQ:
SIO interrupt request bit.
0 = non-request
1 = request.
Bit4
T0IRQ:
T0 Timer interrupt request bit.
0 = non-request
1 = request.
Bit5
TC0IRQ:
TC0 timer interrupt request controls bit.
0 = non request
1 = request.
Bit6
TC1IRQ:
TC1 timer interrupt request controls bit.
0 = non request
1 = request.
When interrupt occurs, the related request bit of INTRQ register will be set to “1” no matter the related enable bit of
INTEN register is enabled or disabled. If the related bit of INTEN = 1 and the related bit of INTRQ is also set to be “1”.
As the result, the system will execute the interrupt vector (ORG 8). If the related bit of INTEN = 0, moreover, the
system won’t execute interrupt vector even when the related bit of INTRQ is set to be “1”. Users need to be cautious
with the operation under multi-interrupt situation.
