SN8P1829
8-Bit MCU build-in 12-bit ADC + PGIA + Charge-pump Reg 128 dots LCD driver
SONiX TECHNOLOGY CO., LTD
Page 26
Version 1.0
PROGRAM FLAG
The PFLAG includes carry flag (C), decimal carry flag (DC) and zero flag (Z). If the result of operating is zero or there is
carry, borrow occurrence, then these flags will set to PFLAG register.
PFLAG initial value = XXXX X000
086H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PFLAG
NT0 NPD -
-
-
C DC
Z
R/W R/W -
-
- R/W R/W R/W
RESET/WAKEUP FLAG
NT0
NPD
Description
0 0
Watchdog timer overflow in sleep mode.
In sleep mode must set “INT_16K_RC” code option as “Always_On” to enable watchdog timer.
0
1
Watchdog timer overflow in normal/slow/green mode.
1 0
Stop system clock (High or Low clock). There are two cases as following:
1. In normal mode: Stop high clock or enter sleep mode (STPHX=1 or CPUM [1:0] = 01)
2. In slow mode: enter sleep mode (CPUM [1:0] = 01)
1
1
External reset or LVD active
Note: Watchdog timer is still running even “Watchdog” code option is disabled. User can disable
watchdog code option then treat NT0/NPD as another timer flag.
CARRY FLAG
C = 1: If executed arithmetic addition with occurring carry signal or executed arithmetic subtraction without borrowing
signal or executed rotation instruction with shifting out logic “1”.
C = 0: If executed arithmetic addition without occurring carry signal or executed arithmetic subtraction with borrowing
signal or executed rotation instruction with shifting out logic “0”.
DECIMAL CARRY FLAG
DC = 1: If executed arithmetic addition with occurring carry signal from low nibble or executed arithmetic subtraction
without borrow signal from high nibble.
DC = 0: If executed arithmetic addition without occurring carry signal from low nibble or executed arithmetic subtraction
with borrow signal from high nibble.
ZERO FLAG
Z = 1: After operation, the content of ACC is zero.
Z = 0: After operation, the content of ACC is not zero.
