SH79F3283
96
Slave 1
Slave 2
SADDR
10100100
10100111
SADEN (bit = 0 will be ignored)
11111010
11111001
Given Address
10100x0x
10100xx1
Broadcast Address (SADDR or SADEN)
1111111x
11111111
The given address for slave 1 and 2 differs in the LSB. For slave 1, it is ignore LSB, while for slave 2 LSB is 1. Thus to
communicate only with slave 1, the master must send an address with LSB = 0 (10100000). Similarly the bit 1 is 0 for slave 1
and ignores the bit 1 for slave 2. Hence to communicate only with slave 2, the master has to transmit an address with bit 1 = 1
(1010 0011). If the master wishes to communicate with both slaves simultaneously, then the address must have bit 0 = 1 and
bit 1 = 0. The bit 2 position is ignored for both the slaves. This allows two different addresses to select both slaves (1010 0001
and 1010 0101).
The master can communicate with all the slaves simultaneously with the Broadcast Address. This address is formed from the
logical OR of the SADDR and SADEN. The zeros in the result are defined as neglect. In most cases, the Broadcast Address is
FFh, this address will be responded by all slaves.
On reset, the SADDR and SADEN are initialized to 00h. The two results set Given Address and Broadcast Address to
XXXXXXXX (all bits are ignored). This effectively removes the multiprocessor communications feature, since any selectivity is
disabled. This ensures that the EUART will reply to any address, which it is compatible with the 80C51 microcontrollers that do
not support automatic address recognition. So the user may implement multiprocessor communication by software recognition
address according to the above mentioned method.
Frame Error Detection
Frame error detection is available when the SSTAT bit in register PCON is set to logic 1.All the 3 error falg bits should be
cleared by software after they are set, even when the following frames received without any error will not be cleared
automatically.
Note: The SSTAT bit must be logic 1 to access any of the status bits (FE, RXOV, and TXCOL). The SSTAT bit must be logic 0
to access the Mode Select bits (SM0, SM1, and SM2).
Transmit Collision
The Transmit Collision bit (TXCOL bit in register SCON) set ‘1’ when a transmission is still in progress and user software
writes data to the SBUF register. If collision occurs, the new data will be ignored and the transmit buffer will not be written.
Receive Overflow
The Receive Overflow bit (RXOV in register SCON) set ‘1’ if a new data byte is latched into the receive buffer before software
has read the previous byte. The previous data is lost when this happen.
Frame Error
The Frame Error bit (FE in register SCON) set ‘1’ if an invalid (low) STOP bit is detected.
Break Detection
A break is detected when any 11 consecutive bits are detected as low. Since a break condition also satisfies the requirements
for a framing error, a break condition will also result in reporting a framing error. Once a break condition has been detected,
the UART will go into an idle state and remain in this idle state until a valid stop bit (rising edge on RxD pin) has been received.
