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Sino Wealth SH79F3283, Manual

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Sino Wealth SH79F3283 Manual Download Page 128

 

SH79F3283

 

128 

 

LOGIC OPERATIONS

 

Opcode 

Description 

Code 

Byte 

Cycle 

ANL A, Rn 

AND register to accumulator 

0x58-0x5F 

1 

1 

ANL A, direct 

AND direct byte to accumulator 

0x55 

2 

2 

ANL A, @Ri 

AND indirect RAM to accumulator 

0x56-0x57 

1 

2 

ANL A, #data 

AND immediate data to accumulator 

0x54 

2 

2 

ANL direct, A 

AND accumulator to direct byte 

0x52 

2 

3 

ANL direct, #data 

AND immediate data to direct byte 

0x53 

3 

3 

ORL A, Rn 

OR register to accumulator 

0x48-0x4F 

1 

1 

ORL A, direct 

OR direct byte to accumulator 

0x45 

2 

2 

ORL A, @Ri 

OR indirect RAM to accumulator 

0x46-0x47 

1 

2 

ORL A, #data 

OR immediate data to accumulator 

0x44 

2 

2 

ORL direct, A 

OR accumulator to direct byte 

0x42 

2 

3 

ORL direct, #data 

OR immediate data to direct byte 

0x43 

3 

3 

XRL A, Rn 

Exclusive OR register to accumulator 

0x68-0x6F 

1 

1 

XRL A, direct 

Exclusive OR direct byte to accumulator 

0x65 

2 

2 

XRL A, @Ri 

Exclusive OR indirect RAM to accumulator 

0x66-0x67 

1 

2 

XRL A, #data 

Exclusive OR immediate data to accumulator 

0x64 

2 

2 

XRL direct, A 

Exclusive OR accumulator to direct byte 

0x62 

2 

3 

XRL direct, #data 

Exclusive OR immediate data to direct byte 

0x63 

3 

3 

CLR A 

Clear accumulator 

0xE4 

1 

1 

CPL A 

Complement accumulator 

0xF4 

1 

1 

RL A 

Rotate accumulator left 

0x23 

1 

1 

RLC A 

Rotate accumulator left through carry 

0x33 

1 

1 

RR A 

Rotate accumulator right 

0x03 

1 

1 

RRC A 

Rotate accumulator right through carry 

0x13 

1 

1 

SWAP A 

Swap nibbles within the accumulator 

0xC4 

1 

4 

 

Summary of Contents for SH79F3283

Page 1: ...n LVR voltage level 1 4 1V LVR voltage level 2 3 7V LVR voltage level 3 2 8V LVR voltage level 4 2 1V CRC verify module built in check size is optional Support SWE simulation write and read CPU Machine cycle 1 oscillator clock Watch Dog Timer WDT Warm up Timer Support Low power operation modes Idle Mode Power Down Mode Flash Type Package TQFP48 LQFP44 LQFP32 2 General Description The SH79F3283 is ...

Page 2: ...errupt Buzzer Power Watch Dog oscillator fail detector 12 bit PWM 8 bit PWM Internal Oscillator Port 3 Configuration I Os Port 4 Configuration I Os P1 0 P1 7 P2 0 P2 7 P0 0 P0 7 Port 2 Configuration I Os P3 0 P3 7 EUART0 1 12 bit ADC Jtag ports for debug Port 5 Configuration I Os LCD LED Driver COM1 8 SEG1 28 Port 1 Configuration I Os P4 0 P4 7 Port 0 Configuration I Os P5 0 P5 5 Oscillator X XTAL...

Page 3: ...PWM01C SEG15 P2 6 FLT SS SEG14 P2 5 SCK SEG13 P2 4 PWM0C SEG16 P2 7 PWM01B SEG17 P0 0 PWM0B SEG18 P0 1 PWM0A T4 P0 3 T2EX INT0 P0 4 XTALX1 INT3 P0 7 XTAL2 P5 1 T2 INT1 P0 5 XTALX2 INT2 P0 6 RST P5 2 XTAL1 P5 0 P3 5 COM6 LED_C6 SGE27 AN5 SH79F3283U P4 5 SEG24 PWM1 34 46 47 48 P4 7 SEG22 LED_S8 SEG8 P1 7 P4 6 SEG23 BUZ T3 P5 3 VDD P5 4 SEG20 P5 5 SEG21 Pin Configuration Diagram TQFP48 Note The out m...

Page 4: ...XD0 SEG10 P2 1 RXD0 SEG9 P2 0 MISO TXD1 SEG12 P2 3 PWM01C SEG15 P2 6 FLT SS SEG14 P2 5 SCK SEG13 P2 4 PWM0C SEG16 P2 7 PWM01B SEG17 P0 0 PWM0B SEG18 P0 1 PWM0A T4 P0 3 T2EX INT0 P0 4 XTALX1 INT3 P0 7 XTAL2 P5 1 T2 INT1 P0 5 XTALX2 INT2 P0 6 RST P5 2 XTAL1 P5 0 P3 5 COM6 LED_C6 SGE27 AN5 SH79F3283P P4 5 SEG24 PWM1 Pin Configuration Diagram LQFP44 Note The out most pin function has the highest prior...

Page 5: ...P1 1 SEG2 LED_S2 INT45 TMS P1 2 SEG3 LED_S3 INT46 TDI TCK INT47 LED_S4 SEG4 P1 3 LED_S5 SEG5 P1 4 RXD0 SEG9 P2 0 TXD0 SEG10 P2 1 FLT SEG14 P2 5 PWM01C SEG15 P2 6 PWM01A SEG19 P0 2 PWM0A T4 P0 3 Pin Configuration Diagram LQFP32 Note The out most pin function has the highest priority and the inner most pin function has the lowest priority Refer to Pin Configuration Diagram This means when one pin is...

Page 6: ...5 P4 5 18 14 9 AVREF AN8 P4 4 P4 4 19 15 10 AN3 INT43 P4 3 P4 3 20 16 11 AN2 INT42 P4 2 P4 2 21 17 12 AN1 INT41 P4 1 P4 1 22 18 13 AN0 INT40 P4 0 P4 0 23 19 14 AN7 SEG25 LED_C8 COM8 P3 7 P3 7 24 20 15 AN6 SEG26 LED_C7 COM7 P3 6 P3 6 25 21 16 AN5 SEG27 LED_C6 COM6 P3 5 P3 5 26 22 17 AN4 SEG28 LED_C5 COM5 P3 4 P3 4 27 23 18 LED_C4 COM4 P3 3 P3 3 28 24 19 LED_C3 COM3 P3 2 P3 2 29 25 20 LED_C2 COM2 P3...

Page 7: ...5 27 RXD0 SEG9 P2 0 P2 0 40 36 28 TXD0 SEG10 P2 1 P2 1 41 37 MOSI RXD1 SEG11 P2 2 P2 2 42 38 MISO TXD1 SEG12 P2 3 P2 3 43 39 SCK SEG13 P2 4 P2 4 44 40 29 FLT SS SEG14 P2 5 P2 5 45 41 30 PWM01C SEG15 P2 6 P2 6 46 42 PWM0C SEG16 P2 7 P2 7 47 43 PWM01B SEG17 P0 0 P0 0 48 44 PWM0B SEG18 P0 1 P0 1 Note P0 4 P0 5 are configured as N channel open drain IO ...

Page 8: ... PWM0A 0B 0C O Output pin for 12 bit PWM0 timer PWM01A 01B 01C O Output pin for 12 bit PWM0 timer with fixed phase relationship of PWM0 FLT I PWM0 Fault Detect input PWM1 O Output pin for 8 bit PWM1 timer EUART RXD0 1 I EUART0 1 data input TXD0 1 O EUART0 1 data output SPI MOSI I O SPI Master output Slave input MISO I O SPI Master input Slave output SCK I O SPI serial clock SS I SPI Slave Select A...

Page 9: ...ut XTALX1 I Oscillator X input XTALX2 O Oscillator X output VSS P Ground VDD P Power supply 2 0 5 5V Buzzer BUZ O Buzzer output pin Programmer TDO P1 0 O Debug interface Test data out TMS P1 1 I Debug interface Test mode select TDI P1 2 I Debug interface Test data in TCK P1 3 I Debug interface Test clock in SWE P1 0 I O Single simulation interface If the power on or down slope of VDD is greater th...

Page 10: ...CLKCON SCMCON Interrupt System Registers IEN0 IEN1 IENC IPH0 IPL0 IPH1 IPL1 EXF0 EXF1 EXCON I O Port Registers P0 P1 P2 P3 P4 P5 P0CR P1CR P2CR P3CR P4CR P5CR P0PCR P1PCR P2PCR P3PCR P4PCR P5PCR P0OS Timer Registers TCON T2CON T2MOD TH2 TL2 RCAP2L RCAP2H T3CON TH3 TL3 T4CON TH4 TL4 SWTHL T5CON TH5 TL5 EUART Registers SCON SBUF SADEN SADDR PCON SCON1 SBUF1 SADEN1 SADDR1 SBRTL SBRTH BFINE SPI Regist...

Page 11: ...0 7 DPL0 6 DPL0 5 DPL0 4 DPL0 3 DPL0 2 DPL0 1 DPL0 0 DPH 83H Data Pointer High byte 00000000 DPH0 7 DPH0 6 DPH0 5 DPH0 4 DPH0 3 DPH0 2 DPH0 1 DPH0 0 DPL1 84H Data Pointer 1 Low byte 00000000 DPL1 7 DPL1 6 DPL1 5 DPL1 4 DPL1 3 DPL1 2 DPL1 1 DPL1 0 DPH1 85H Data Pointer 1 High byte 00000000 DPH1 7 DPH1 6 DPH1 5 DPH1 4 DPH1 3 DPH1 2 DPH1 1 DPH1 0 INSCON 86H Data pointer select 0 00 0 BKS0 DIV MUL DPS...

Page 12: ...Flash Memory Control Register 3 0000 IB_CON3 3 IB_CON3 2 IB_CON3 1 IB_CON3 0 IB_CON4 F5H Bank0 Flash Memory Control Register 4 0000 IB_CON4 3 IB_CON4 2 IB_CON4 1 IB_CON4 0 IB_CON5 F6H Bank0 Flash Memory Control Register 5 0000 IB_CON5 3 IB_CON5 2 IB_CON5 1 IB_CON5 0 XPAGE F7H Bank0 Memory Page 0000000 XPAGE 6 XPAGE 5 XPAGE 4 XPAGE 3 XPAGE 2 XPAGE 1 XPAGE 0 FLASHCON A7H Bank0 Flash access control 0...

Page 13: ...SCM ELPD IPH0 B4H Bank0 Interrupt Priority Control High 0 0000000 PADCH PT2H PSH PCMPH PX1H PT5H PX0H IPL0 B8H Bank0 Interrupt Priority Control Low 0 0000000 PADCL PT2L PSL PCMPL PX1L PT5L PX0L IPH1 B5H Bank0 Interrupt Priority Control High 1 00000000 PSCMH PT4H PPWMH PT3S1H PX4H PX3H PX2H PSPIH IPL1 B9H Bank0 Interrupt Priority Control Low 1 00000000 PSCML PT4L PPWML PT3S1L PX4L PX3L PX2L PSPIL E...

Page 14: ...4H Bank0 Port3 input output direction control 00000000 P3CR 7 P3CR 6 P3CR 5 P3CR 4 P3CR 3 P3CR 2 P3CR 1 P3CR 0 P4CR E5H Bank0 Port4 input output direction control 00000000 P4CR 7 P4CR 6 P4CR 5 P4CR 4 P4CR 3 P4CR 2 P4CR 1 P4CR 0 P5CR E1H Bank1 Port5 input output direction control 000000 P5CR 5 P5CR 4 P5CR 3 P5CR 2 P5CR 1 P5CR 0 P0PCR E9H Bank0 Internal pull high enable for Port0 00000000 P0PCR 7 P0...

Page 15: ...0000000 TH2 7 TH2 6 TH2 5 TH2 4 TH2 3 TH2 2 TH2 1 TH2 0 T3CON 88H Bank1 Timer Counter 3 Control 0 00 000 TF3 T3PS 1 T3PS 0 TR3 T3CLKS 1 T3CLKS 0 SWTHL 89H Bank1 Timer Counter data switch 00 T5HLCON T3HLCON TL3 8CH Bank1 Timer Counter 3 Low Byte 00000000 TL3 7 TL3 6 TL3 5 TL3 4 TL3 3 TL3 2 TL3 1 TL3 0 TH3 8DH Bank1 Timer Counter 3 High Byte 00000000 TH3 7 TH3 6 TH3 5 TH3 4 TH3 3 TH3 2 TH3 1 TH3 0 T...

Page 16: ...uffer 00000000 SBUF1 7 SBUF1 6 SBUF1 5 SBUF1 4 SBUF1 3 SBUF1 2 SBUF1 1 SBUF1 0 SADEN1 9AH Bank1 EUART1 Slave Address Mask 00000000 SADEN1 7 SADEN1 6 SADEN1 5 SADEN1 4 SADEN1 3 SADEN1 2 SADEN1 1 SADEN1 0 SADDR1 9BH Bank1 EUART1 Slave Addres 00000000 SADDR1 7 SADDR1 6 SADDR1 5 SADDR1 4 SADDR1 3 SADDR1 2 SADDR1 1 SADDR1 0 SBRTH 9DH Bank1 EUART1 Baudrate Generator 00000000 SBRTEN SBRT 14 SBRT 13 SBRT ...

Page 17: ...e POR WDT LVR PIN Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 BUZCON BDH Bank0 Buzzer output control 0000 BCA2 BCA1 BCA0 BZEN Table 6 13 LCD SFRs Mnem Add Name POR WDT LVR PIN Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DISPCON ABH Bank0 LCD Control 00000000 DISPSEL LCDON ELCC DUTY0 VOL3 VOL2 VOL1 VOL0 DISPCON1 ADH Bank0 LCD Control 1 00000000 MODSW DUTY2 DUTY1 RLCD FCCTL1 FCCTL0 M...

Page 18: ...O 4 PWMLO 3 PWMLO 2 PWMLO 1 PWMLO 0 PWM0C D2H Bank0 12 bit PWM0 Control 00000000 PWM0IE PWM0IF TnCK02 FLTS FLTC PWM0S TnCK01 TnCK00 PWM0PL D3H Bank0 12 bit PWM0 Period Control low byte 00000000 PP0 7 PP0 6 PP0 5 PP 4 PP0 3 PP0 2 PP0 1 PP0 0 PWM0PH D4H Bank0 12 bit PWM0 Period Control high byte 0000 PP0 11 PP0 10 PP0 9 PP0 8 PWM0DL D5H Bank0 12 bit PWM0 Duty Control low byte 00000000 PD0 7 PD0 6 PD...

Page 19: ...17 CRC SFRs Mnem Add Name POR WDT LVR PIN Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CRCCON FDH Bank0 CRC verify control 00 0000 CRC_GO CRCIF CRCADR3 CRCADR2 CRCADR1 CRCADR0 CRCDL F9H Bank0 CRC verify result low byte 00000000 CRCD7 CRCD6 CRCD5 CRCD4 CRCD3 CRCD2 CRCD1 CRCD0 CRCDH FAH Bank0 CRC verify result high byte 00000000 CRCD15 CRCD14 CRCD13 CRCD12 CRCD11 CRCD10 CRCD9 CRCD8 Note Unimp...

Page 20: ...7H A8H IEN0 IEN1 DISPCLK1 DISPCON DISPCLK0 DISPCON1 AFH A0H P2 SCMCON SPCON SPDAT ISPLO ISPCON FLASHCON A7H 98H SCON SBUF SADDR SADEN P1SS P2SS P3SS 9FH 90H P1 ADCON1 ADCON ADT ADCH ADDL ADDH 97H 88H TCON EXCON SUSLO 8FH 80H P0 SP DPL DPH DPL1 DPH1 INSCON PCON 87H 0 8 1 9 2 A 3 B 4 C 5 D 6 E 7 F Bank1 Bit addressable Non Bit addressable 0 8 1 9 2 A 3 B 4 C 5 D 6 E 7 F F8H FFH F0H B AUXC XPAGE F7H ...

Page 21: ...unction is to hold a 16 bit address but it may be manipulated as a 16 bit register or as two independent 8 bit registers Table 7 1 PSW Register D0H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PSW CY AC F0 RS1 RS0 OV F1 P R W R W R W R W R W R W R W R W R Reset Value POR WDT LVR PIN 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7 CY Carry flag bit 0 no carry or borrow in an arithmetic or logic op...

Page 22: ... Remainder INSCON 3 1 16 bit mode AUXC A B Quotient Low Byte Remainder Quotient High Byte Dual Data Pointer Using two data pointers can accelerate data memory moves The standard data pointer is called DPTR and the new data pointer is called DPTR1 DPTR1 is similar to DPTR which consists of a high byte DPH1 and a low byte DPL1 Its intended function is to hold a 16 bit address but it may be manipulat...

Page 23: ...nal data space Also SH79F3283 provides 28 bytes LCD RAM 500H 51BH 51BH 7FH 80H 0FFH 0FFH 80H 00H 00H Upper 128 bytes Internal Ram indirect accesses Lower 128 bytes Internal Ram direct or indirect accesses Extenal RAM SFR Bank0 direct accesses 500H 4FFH LCD RAM SFR Bank1 direct accesses 80H 0FFH The Internal and External RAM Configuration The SH79F3283 provides traditional method for accessing of e...

Page 24: ...er to wipe the Flash memory read and write operations Self Sector Programming SSP mode User Program code run in Program Memory to wipe the flash memory read and write operations Flash Memory Supports the Following Operations 1 Code Protection Control Mode SH79F3283 code protection function provides a high performance security measures for the user Each partition has four modes are available Code p...

Page 25: ...ory block erasure instruction to run EEPROM like memory block erasure see chapter SSP 5 Write Read Code Write read code operation can read or write code from flash memory block The user program SSP and Flash programmer can perform this operation For user programs to perform the operation code protection mode 1 in the selected sector must be forbidden Regardless of the security bit Settings or not ...

Page 26: ...ption please refers to the FLASH Programmer s user guide In ICP mode all the flash operations are completed by the programmer through 6 wire interface Since the program signal is very sensitive 6 jumpers are needed VDD GND TDO SWE TDI TCK TMS to separate the program pins from the application circuit as show in the following diagram Four JTAG Pins Mode MCU TCK TDI TDO GND To Application Circuit Jum...

Page 27: ...ry Page Register for Programming For EEPROM like memory one sector is 256 bytes F7H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 XPAGE XPAGE 6 XPAGE 5 XPAGE 4 XPAGE 3 XPAGE 2 XPAGE 1 XPAGE 0 R W R W R W R W R W R W R W R W Reset Value POR WDT LVR PIN 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 6 2 XPAGE 6 2 Reserved 1 0 XPAGE 1 0 Sector of the flash memory to be programmed 00 means sector 0 and s...

Page 28: ... SSP Flow Control Register2 F4H Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IB_CON3 IB_CON3 3 IB_CON3 2 IB_CON3 1 IB_CON3 0 R W R W R W R W R W Reset Value POR WDT LVR PIN 0 0 0 0 Bit Number Bit Mnemonic Description 3 0 IB_CON3 3 0 Must be 0AH otherwise Flash Programming will terminate Table 7 11 SSP Flow Control Register3 F5H Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IB_CON4 IB_CON4 3 IB_CO...

Page 29: ...9H IB_CON5 6H IB_CON1 6EH IB_CON2 3 0 5H IB_CON3 AH IB_CON4 9H IB_CON5 6H Programming Set IB_OFFSET Set XPAGE Set IB_DATA Set IB_CON1 IB_CON2 5H IB_CON2 3 0 5H Set IB_CON2 3 0 5H IB_CON3 AH Set IB_CON3 AH IB_CON3 AH Set IB_CON4 9H IB_CON4 9H Set IB_CON5 6H IB_CON2 5H ELSE Sector Erase Reset IB_CON1 5 ...

Page 30: ...ctor Erase CPU will be in IDLE mode 6 Go to step 2 if more sectors are to be erased 7 Clear XPAGE enable interrupt if necessary 3 For Code Reading Just Use MOVC A A DPTR or MOVC A A PC 4 For EEPROM Like Step is same as code programming the differences are 1 Set FAC bit in FLASHCON register before programming or erase EEPROM Like 2 One sector of EEPROM Like is 256 bytes not 1024 bytes Note 1 The sy...

Page 31: ...defined as the SYSCLK frequency tSYS is defined as the SYSCLK period 7 5 3 Description SH79F3283 has six oscillator types 32 768kHz crystal oscillator crystal oscillator ceramic oscillator 2MHz 16MHz and internal RC 16MHz 12MHz 8MHz 128KHz which is selected by code option OP_OSC Refer to code option section for details SH79F3283 has 4 oscillator pins XTAL1 XTAL2 XTALX1 XTALX2 which can generate 1 ...

Page 32: ... is selected refer to code option section Note 1 If code option OP_OSC is 0011 1010 OSCXCLK is Internal 12M RC if code option OP_OSC is 0110 1101 OSCXCLK is oscillator from XTALX1 input 2 HFON and FS is valid only when code option OP_OSC is 0011 0110 1010 1101 3 When OSCXCLK is used as OSCSCLK that is HFON 1 and FS 1 HFON is can t be cleared by software 4 When OSCSCLK changed from 32 768kHz 128kHz...

Page 33: ...TAL2 C1 C2 32 768kHz 3 OP_OSC 1101 32 768kHz Crystal Oscillator at XTAL 2M 12M Crystal Ceramic oscillator from XTALX input XTALX1 XTALX2 XTAL1 XTAL2 C1 C2 32 768kHz C1 C2 Crystal Ceramic 4 OP_OSC 1110 2M 12M Crystal Ceramic oscillator from XTAL input XTALX shared with IO XTALX1 XTALX2 XTAL1 XTAL2 C1 C2 Crystal Ceramic 5 OP_OSC 0110 128kHz internal RC 2M 12M Crystal Ceramic oscillator from XTAL inp...

Page 34: ...ted with the crystals listed above for basic start up and operation They are not optimized 3 Be careful for the stray capacitance on PCB board the user should test the performance of the oscillator over the expected VDD and the temperature range for the application 4 Before selecting crystal ceramic the user should consult the crystal ceramic manufacturer for appropriate value of external componen...

Page 35: ...ock only Notes The SCMIF is read only register it can be clear to 0 or set to 1 by hardware only If SCMIF is cleared the SCM switches the system clock to the state before system clock breaks down automatically If Internal RC is selected as OSCSCLK by code option Refer to code option section for detail the SCM can not work Table 7 15 System Clock Control Register B2H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 B...

Page 36: ... 0 P4CR E5H Bank0 P4CR 7 P4CR 6 P4CR 5 P4CR 4 P4CR 3 P4CR 2 P4CR 1 P4CR 0 P5CR E1H Bank1 P5CR 5 P5CR 4 P5CR 3 P5CR 2 P5CR 1 P5CR 0 R W R W R W R W R W R W R W R W R W Reset Value POR WDT LVR PIN 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7 0 PxCRy x 0 5 y 0 7 Port input output control Register 0 input mode 1 output mode Table 7 18 Port Pull up Resistor Control Register E9H ECH Bit7 Bit6 B...

Page 37: ...3 P5 2 P5 1 P5 0 R W R W R W R W R W R W R W R W R W Reset Value POR WDT LVR PIN 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7 0 Px y x 0 5 y 0 7 Port Data Register Table 7 20 Port mode select Register EFH Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0OS P0OS 5 P0OS 4 R W R W R W Reset Value POR WDT LVR PIN 0 0 Bit Number Bit Mnemonic Description 5 4 P0OS x x 5 4 Port0 output mode select...

Page 38: ...guration has the highest priority and the inner most pin function has the lowest priority This means when one pin is occupied by a higher priority function if enabled it cannot be used as the lower priority functional pin even the lower priority function is also enabled Only until the higher priority function is closed by hardware or software can the corresponding pin be released for the lower pri...

Page 39: ...ON register Auto Pull up or clear T4CLKS bit and set TC4 bit or set TR4 bit in Mode2 3 P0 3 Above condition is not met 3 3 1 T2EX In mode 0 2 3 set EXEN2 bit in T2CON register or in mode 1 set DCEN bit in T2MOD register or in mode 1 clear DCEN bit and set EXEN2 bit Auto Pull up 2 INT0 Set EX0 bit in IEN0 Register and Port0 4 is in input mode 3 P0 4 Above condition is not met 4 4 1 T2 Set TR2 bit a...

Page 40: ...P2 0 TXD0 EUART0 data output P2 1 MOSI SPI Master output Slave input P2 2 MISO SPI Master input Slave output P2 3 SCK SPI Serial Clock P2 4 FLT Fault input pin P2 5 LCD Segment 9 16 P2 0 P2 7 SS SPI Slave selection P2 5 PWM0C PWM0C output P2 7 PWM01C PWM01C output P2 6 Table 7 23 PORT2 Share Table Pin No Priority Function Enable bit TQFP48 LQFP44 LQFP32 39 35 27 1 RXD0 Set REN bit in SCON Register...

Page 41: ...1C Set EPWM1 bit and PWM01COE bit in PWMEN Register 2 SEG15 Clear DISPSEL bit in DISPCON Register and set P2S6 in P2SS Register 3 P2 6 Above condition is not met 46 42 1 PWM0C Set EPWM1 bit and PWM01COE bit in PWMEN Register 2 SEG16 Clear DISPSEL bit in DISPCON Register and set P2S7 in P2SS Register 3 P2 7 Above condition is not met PORT3 LED COM1 COM8 P3 0 P3 7 LCD COM1 COM8 P3 0 P3 7 AN4 AN7 ADC...

Page 42: ...r 2 AN8 Set CH8 bit in ADCH Register and set SCH 2 0 3 P4 4 Above condition is not met 19 15 10 1 AN3 Set CH3 bit in ADCH Register and set SCH 2 0 2 INT43 Set EX4 bit in IEN1 register and set EXS43 bit in IENC register P4 3 in input mode 3 P4 3 Above condition is not met 20 16 11 1 AN2 Set CH2 bit in ADCH Register and set SCH 2 0 2 INT42 Set EX4 bit in IEN1 register and set EXS42 bit in IENC regis...

Page 43: ...on is not met 9 9 5 1 XTAL2 Selected by Code Option 2 P5 1 Above condition is not met 10 10 6 1 RST Selected by Code Option 2 P5 2 Selected by Code Option 11 11 7 1 BUZ Set BZEN bit in BUZCON register 2 T3 Set TR3 bit in T3CON register and T3CLKS 1 0 01 Auto Pull up 3 P5 3 Above condition is not met 13 1 SEG20 Set P5S4 bits in P0SS register set DISPSEL bit and DUTY bit in DISPCON register 2 P5 4 A...

Page 44: ...ination of RCLK TCLK and CP RL2 Table 7 27 Timer2 Mode select C T2 T2OE DCEN TR2 CP RL2 RCLK TCLK MODE X 0 X 1 1 0 0 0 16 bit capture X 0 0 1 0 0 0 1 16 bit auto reload timer X 0 1 1 0 0 0 X 0 X 1 X 1 X 2 Baud Rate generator X 1 0 1 X 1 X 0 0 3 Programmable clock output only 1 X 3 Programmable clock output with Baud Rate generator X 1 1 1 X 1 X X X Not recommending X X X 0 X X X X Timer2 stops the...

Page 45: ...h On Increment Mode 0 Switch Off 1 Switch On External Falling Edge flag TL2 TH2 T2EX T2 Interrupt Request Overflow Flag TR2 EXEN2 1 12 System Clock TCLKP2 Setting the DCEN bit enables Timer2 to count up or down When DCEN 1 the T2EX pin controls the direction of the count and EXEN2 s control is invalid A logical 1 at T2EX makes Timer2 count up The timer will overflow at 0FFFFH and set the TF2 bit T...

Page 46: ... this will not generate an interrupt If EXEN2 is set a 1 to 0 transition in T2EX will set EXF2 but will not cause a reload Thus when Timer2 is in use as a baud rate generator T2EX can be used as an extra external interrupt The baud rate in EUART mode 1 3 is determined by the timer 2 overflow ratio according to the following equation RCAP2L RCAP2H 65536 SYS f 16 2 1 BaudRate C T2 0 RCAP2L RCAP2H 65...

Page 47: ...le Clock output Mode 3 of Timer2 T2 T2OE TL2 TH2 RCAP2L RCAP2H EXEN2 EXF2 0 Switch Off 1 Switch On T2EX C T2 C T2 2 0 Switch Off 1 Switch On Timer2 Interrupt Request 0 Switch Off 1 Switch On 1 12 System Clock TCLKP2 1 2 Note 1 Both TF2 and EXF2 can cause timer2 interrupt request and they have the same vector address 2 TF2 and EXF2 are set as 1 by hardware while event occurs But they can also be se...

Page 48: ...nerates receiving baud rate 1 Timer2 generates receiving baud rate 4 TCLK EUART0 Transmit Clock control bit 0 Timer4 generates transmitting baud rate 1 Timer2 generates transmitting baud rate 3 EXEN2 External event input falling edge from T2EX pin used as Reload Capture trigger enable disable control bit 0 Ignore events on T2EX pin 1 Cause a capture or reload when a negative edge on T2EX pin is de...

Page 49: ...sable Timer2 as up down counter Timer2 is an up counter 1 Enable Timer2 as up down counter Table 7 30 Timer2 Reload Capture Data Registers CAH CDH Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RCAP2L RCAP2L 7 RCAP2L 6 RCAP2L 5 RCAP2L 4 RCAP2L 3 RCAP2L 2 RCAP2L 1 RCAP2L 0 RCAP2H RCAP2H 7 RCAP2H 6 RCAP2H 5 RCAP2H 4 RCAP2H 3 RCAP2H 2 RCAP2H 1 RCAP2H 0 TL2 TL2 7 TL2 6 TL2 5 TL2 4 TL2 3 TL2 2 TL2 1 TL2...

Page 50: ...n High bits first Low bits followed TF3 The Block Diagram of Timer3 TL3 TH3 Increment Mode 0 Switch Off 1 Switch On 16 bit Counter Interrupt Request Overflow Flag TR3 System Clock Prescaler 1 8 64 256 T3PS 1 0 T3CLKS 1 0 00 01 10 T3 32 768kHz Crystal Timer3 can operate in Power Down mode When OP_OSC 3 0 Refer to Code Option Section for details is 1010 1101 0011 or 0110 T3CLKS 1 0 can select 00 or ...

Page 51: ...xternal clock from pin T3 auto pull up 10 External 32 768kHz crystal or internal 128kHZ RC 11 reserved Table 7 32 Timer3 Reload Counter Data Registers 8CH 8DH Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TL3 TL3 7 TL3 6 TL3 5 TL3 4 TL3 3 TL3 2 TL3 1 TL3 0 TH3 TH3 7 TH3 6 TH3 5 TH3 4 TH3 3 TH3 2 TH3 1 TH3 0 R W R W R W R W R W R W R W R W R W Reset Value POR WDT LVR PIN 0 0 0 0 0 0 0 0 Bit Number ...

Page 52: ...rupt will occur if Timer 4 interrupts is enabled The T4CLKS bit T4CON 0 selects the counter timer s clock source If T4CLKS 1 external clock from the Pin T4 is selected as Timer4 clock after prescaled it will increase the Counter Timer4 Data register Else if T4CLKS 0 the system clock is selected as Timer4 clock Setting the TR4 bit T4CON 1 enables the timer Setting TR4 does not clear the counter dat...

Page 53: ...register and Timer4 holds and waits the next trig edge When Timer4 is working an active trig signal maybe come if TC4 0 the trig signal will be ignored if TC4 1 Timer4 will be re trigged Setting TR4 does not clear the counter data of Timer4 The timer register should be loaded with the desired initial value before the timer is enabled TF4 The Block Diagram of Mode 2 of Timer 4 TL4 TH4 Increment Mod...

Page 54: ...mer4 Mode Select bit 00 Mode0 16 bit auto reload timer 01 Mode1 baud rate generator for EUART 10 Mode2 with rising edge trig from pin T4 system clock only T4CLKS is invalid 11 Mode2 with falling edge trig from pin T4 system clock only T4CLKS is invalid 1 TR4 Timer4 start stop control bit 0 Stop Timer4 1 Start Timer4 0 T4CLKS Timer4 Clock Source select bit 0 System clock T4 pin is used as I O port ...

Page 55: ...se steps Write operation Low bits first High bits followed Read operation High bits first Low bits followed Timer5 Modes Timer5 has one operating modes 16 bit auto reload timer Mode0 16 bit Auto Reload Counter Timer Timer5 operates as 16 bit counter timer in Mode 0 The TH5 register holds the high eight bits of the 16 bit counter timer TL5 holds the low eight bits As the 16 bit timer register incre...

Page 56: ...able 7 37 Timer5 Reload Counter Data Registers CEH CFH Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TL5 TL5 7 TL5 6 TL5 5 TL5 4 TL5 3 TL5 2 TL5 1 TL5 0 TH5 TH5 7 TH5 6 TH5 5 TH5 4 TH5 3 TH5 2 TH5 1 TH5 0 R W R W R W R W R W R W R W R W R W Reset Value POR WDT LVR PIN 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7 0 TL5 x Timer5 Low High byte counter x 0 7 TH5 x Table 7 38 Timer5 Reload Cou...

Page 57: ...h means that all the interrupts are disabled 7 9 3 Register Table 7 39 Primary Interrupt Enable Register A8H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IEN0 EA EADC ET2 ES0 EX1 ET5 EX0 R W R W R W R W R W R W R W R W Reset Value POR WDT LVR PIN 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7 EA All interrupt enable bit 0 Disable all interrupt 1 Enable all interrupt 6 EADC ADC interrupt enable bit...

Page 58: ...S1 Timer3 EUART0 overflow interrupt enable bit 0 Disable timer3 EUART0 overflow interrupt 1 Enable timer3 EUART0 overflow interrupt 3 EX4 External interrupt4 enable bit 0 Disable external interrupt4 1 Enable external interrupt4 2 EX3 External interrupt3 enable bit 0 Disable external interrupt3 1 Enable external interrupt3 1 EX2 External interrupt2 enable bit 0 Disable external interrupt2 1 Enable ...

Page 59: ...rrupt channel Enable Register1 BBH Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IENC1 ECRC ES1 ET3 ESCM ELPD R W R W R W R W R W R W Reset Value POR WDT LVR PIN 0 0 0 0 0 Bit Number Bit Mnemonic Description 6 ECRC CRC interrupt enable bit 0 Disable CRC interrupt 1 Enable CRC interrupt 5 ES1 EUART1 interrupt enable bit 0 Disable EUART1 interrupt 1 Enable EUART1 interrupt 4 ET3 Timer3 interrupt ena...

Page 60: ...errupt The EUARTx x 0 1 interrupts is generated by the logical OR of flag RI and TI in SCON SCON1 register which is set by hardware Neither of these flags can be cleared by hardware when the service routine is vectored In fact the service routine will normally have to determine whether it was the receive interrupt flag or the transmission interrupt flag that generated the interrupt so the flag mus...

Page 61: ...n falling edge 10 Trigger on rising edge 11 Trigger on both edge 3 2 IT2 1 0 External interrupt2 trigger mode selection bit 00 Low Level trigger 01 Trigger on falling edge 10 Trigger on rising edge 11 Trigger on both edge 1 IE3 External interrupt3 request flag bit 0 No interrupt pending 1 Interrupt is pending 0 IE2 External interrupt2 request flag bit 0 No interrupt pending 1 Interrupt is pending ...

Page 62: ...iority levels are received simultaneously the request of higher priority level is serviced If the same priority interrupt source apply for the interrupt at the beginning of the instruction cycle at the same time an internal polling sequence determines which request is serviced Interrupt Priority Priority bits Interrupt Lever Priority IPHx IPLx 0 0 Level 0 lowest priority 0 1 Level 1 1 0 Level 2 1 ...

Page 63: ... service execution proceeds from that location until the RETI instruction is encountered The RETI instruction informs the processor that the interrupt routine is no longer in progress and then pops the top two bytes from the stack and reloads the program counter Execution of the interrupted program continues from the point where it was stopped The RET instruction can also return to the original ad...

Page 64: ...interrupt4 operates in the similar ways except have different registers and have more selection of trigger If the external interrupt is level triggered the external source must hold the request active until the requested interrupt is generated which will take 2 machine cycles If the external interrupt is still asserted when the interrupt service routine is completed another interrupt will be gener...

Page 65: ... Bit Number Bit Mnemonic Description 7 6 I1PS 1 0 INT4 sample clock Prescaler Select bits 00 1 1 01 1 4 10 1 16 11 1 64 5 4 I1SN 1 0 INT4 sample times Select bits 00 1 01 2 10 3 11 4 3 2 I0PS 1 0 INT0 1 2 3 sample clock Prescaler Select bits 00 1 1 01 1 4 10 1 16 11 1 64 1 0 I0SN 1 0 INT0 1 2 3 sample times Select bits 00 1 01 2 10 3 11 4 Note If I0SN 1 0 11 the INT0 1 2 3 falling edge trigger nee...

Page 66: ...F5 2 1 INT1 0013H EX1 IE1 3 2 EUART0 0023H ES0 RI TI 5 4 Timer2 002BH ET2 TF2 EXF2 6 5 ADC 0033H EADC ADCIF 7 6 SPI 003BH ESPI SPIF 8 7 INT2 0043H EX2 IE2 9 8 INT3 004BH EX3 IE3 10 9 INT4 0053H EX4 IENC IF43 40 11 10 Timer3 005BH ET3 ET3_ES1 TF3 12 11 PWM 0063H EPWM PWM0 1IF 13 12 Timer4 006BH ET4 TF4 14 13 SCM LPD CRC 0073H ESCM ELPD ECRC ESCM_LPD_CRC SCMIF LPDF CRCIF 15 lowest 14 ...

Page 67: ...Hz When OP_OSC 3 0 is 0000 0001 1110 in stop mode the LCD clock will be turned off When OP_OSC 3 0 is 0011 0100 0110 1010 1011 1101 and MCU worked in high frequency mode in stop mode the LCD clock is still working When OP_OSC 3 0 is 0011 0100 0110 1010 1011 1101 and MCU worked in low frequency mode in stop mode the LCD clock will be turned off and the LCD clock is still working in IDLE mode LCD wo...

Page 68: ...F3283 68 SEGn V3 COM4 SEGn SEGn 1 0 COM4 COM3 COM2 COM1 COM4 COM3 COM2 COM1 V2 V1 V3 0 V2 V1 V3 0 V2 V1 V3 0 V2 V1 V3 0 V2 V1 V 0 V2 V1 V3 0 V V1 V3 V2 V1 SEGn 1 SEGn one frame LCD Waveform 1 4duty 1 3bias ...

Page 69: ...9 V3 V2 V1 0 SEGn COM2 COM1 VDD COM3 COM4 COM8 COM6 COM3 COM1 COM5 COM7 COM2 SEGn V3 V2 V1 0 VDD V3 V2 V1 0 VDD V3 V2 V1 0 VDD V3 V2 V1 0 VDD V3 V2 V1 0 VDD COM4 COM1 SEGn V2 V3 V1 VDD LCD Waveform 1 8duty 1 4bias ...

Page 70: ...CD contrast on off control bit 0 disable contrast 1 enable contrast 4 DUTY0 LCD duty selection bit Combination control with DUTY 2 1 Refer to DUTY 2 1 3 0 VOL 3 0 LCD contrast control bits 0000 VLCD 0 531VDD 0001 VLCD 0 563VDD 0010 VLCD 0 594VDD 0011 VLCD 0 625VDD 0100 VLCD 0 656VDD 0101 VLCD 0 688VDD 0110 VLCD 0 719VDD 0111 VLCD 0 750VDD 1000 VLCD 0 781VDD 1001 VLCD 0 813VDD 1010 VLCD 0 844VDD 10...

Page 71: ... COM6 8 shared as SEG25 27 100 1 6 duty 1 3 bias 6 COM X 26 SEG COM COM1 6 SEG SEG1 24 COM7 8 shared as SEG25 SEG26 101 1 6 duty 1 4 bias 6 COM X 26 SEG COM COM1 6 SEG SEG1 24 COM7 8 shared as SEG25 SEG26 others 1 4 duty 1 3 bias 4 COM X 28 SEG COM COM1 4 SEG SEG1 28 4 RLCD LCD bias resistor control bit 0 LCD bias resistor sum is 225k 1 LCD bias resistor sum is 900k 3 2 FCCTL 1 0 Fast charge time ...

Page 72: ...en OP_OSC 3 0 is others LCD clock source is 128kHz set DCK 1 0 bits in DISPCLK0 register select 1 4 1 3 1 2 1 1 prescaler so that the LCD frame is 256 4Hz 256 3Hz 256 2Hz 256 1Hz Table 8 4 Px Mode Select Register B6H Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0SS P4S7 P4S6 P4S5 P5S5 P5S4 P0S2 P0S1 P0S0 R W R W R W R W R W R W R W R W R W Reset Value POR WDT LVR PIN 0 0 0 0 0 0 0 0 Bit Number B...

Page 73: ...t2 Bit1 Bit0 P2SS P2S7 P2S6 P2S5 P2S4 P2S3 P2S2 P2S1 P2S0 R W R W R W R W R W R W R W R W R W Reset Value POR WDT LVR PIN 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7 0 P2S 7 0 P2 mode select bit 0 P2 0 P2 7 is I O 1 P2 0 P2 7 shared as Segment SEG9 SEG16 Table 8 7 P3 mode select register 9EH Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P3SS P3S7 P3S6 P3S5 P3S4 P3S3 P3S2 P3S1 P3S0 R W R ...

Page 74: ... 509H SEG10 SEG10 SEG10 SEG10 50AH SEG11 SEG11 SEG11 SEG11 50BH SEG12 SEG12 SEG12 SEG12 50CH SEG13 SEG13 SEG13 SEG13 50DH SEG14 SEG14 SEG14 SEG14 50EH SEG15 SEG15 SEG15 SEG15 50FH SEG16 SEG16 SEG16 SEG16 510H SEG17 SEG17 SEG17 SEG17 511H SEG18 SEG18 SEG18 SEG18 512H SEG19 SEG19 SEG19 SEG19 513H SEG20 SEG20 SEG20 SEG20 514H SEG21 SEG21 SEG21 SEG21 515H SEG22 SEG22 SEG22 SEG22 516H SEG23 SEG23 SEG23...

Page 75: ...G10 SEG10 SEG10 50AH SEG11 SEG11 SEG11 SEG11 SEG11 SEG11 SEG11 SEG11 50BH SEG12 SEG12 SEG12 SEG12 SEG12 SEG12 SEG12 SEG12 50CH SEG13 SEG13 SEG13 SEG13 SEG13 SEG13 SEG13 SEG13 50DH SEG14 SEG14 SEG14 SEG14 SEG14 SEG14 SEG14 SEG14 50EH SEG15 SEG15 SEG15 SEG15 SEG15 SEG15 SEG15 SEG15 50FH SEG16 SEG16 SEG16 SEG16 SEG16 SEG16 SEG16 SEG16 510H SEG17 SEG17 SEG17 SEG17 SEG17 SEG17 SEG17 SEG17 511H SEG18 SE...

Page 76: ...SEG10 50AH SEG11 SEG11 SEG11 SEG11 SEG11 50BH SEG12 SEG12 SEG12 SEG12 SEG12 50CH SEG13 SEG13 SEG13 SEG13 SEG13 50DH SEG14 SEG14 SEG14 SEG14 SEG14 50EH SEG15 SEG15 SEG15 SEG15 SEG15 50FH SEG16 SEG16 SEG16 SEG16 SEG16 510H SEG17 SEG17 SEG17 SEG17 SEG17 511H SEG18 SEG18 SEG18 SEG18 SEG18 512H SEG19 SEG19 SEG19 SEG19 SEG19 513H SEG20 SEG20 SEG20 SEG20 SEG20 514H SEG21 SEG21 SEG21 SEG21 SEG21 515H SEG2...

Page 77: ... SEG10 50AH SEG11 SEG11 SEG11 SEG11 SEG11 SEG11 50BH SEG12 SEG12 SEG12 SEG12 SEG12 SEG12 50CH SEG13 SEG13 SEG13 SEG13 SEG13 SEG13 50DH SEG14 SEG14 SEG14 SEG14 SEG14 SEG14 50EH SEG15 SEG15 SEG15 SEG15 SEG15 SEG15 50FH SEG16 SEG16 SEG16 SEG16 SEG16 SEG16 510H SEG17 SEG17 SEG17 SEG17 SEG17 SEG17 511H SEG18 SEG18 SEG18 SEG18 SEG18 SEG18 512H SEG19 SEG19 SEG19 SEG19 SEG19 SEG19 513H SEG20 SEG20 SEG20 S...

Page 78: ...ty when OP_P37 P34 0 and OP_P33 P 0 1 the Port3 large current sink ability is enable Refer to Code Option During the Power in Reset Pin Reset LVR Reset and Watchdog Reset the LED driver will be turned off 8 2 1 Register Table 8 8 LED Control Register ABH Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DISPCON DISPSEL LEDON DUTY0 R W R W R W R W Reset Value POR WDT LVR PIN 0 0 0 Bit Number Bit Mnemon...

Page 79: ...can continue when OP_MODSW 1 the LCD counter data scan stop keep the data continue scan when MODSW 0 Table 8 10 LED Clock Control Register ACH Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DISPCLK0 DCK0 1 DCK0 0 R W R W R W Reset Value POR WDT LVR PIN 0 0 Bit Number Bit Mnemonic Description 1 0 DCK 1 0 LED clock prescaler select bit 00 1 4 prescaler 01 1 3 prescaler 10 1 2 prescaler 11 1 1 prescal...

Page 80: ...s I O 1 P3 0 P3 7 shared as Common LED_C1 LED_C8 8 2 2 Configuration of LED RAM LED 1 3 duty LED_C1 3 LED_S1 8 Address 7 6 5 4 3 2 1 0 500H COM1 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 501H COM2 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 502H COM3 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 LED 1 4 duty LED_C1 4 LED_S1 8 Address 7 6 5 4 3 2 1 0 500H COM1 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 501H COM2 ...

Page 81: ...G6 SEG5 SEG4 SEG3 SEG2 SEG1 505H COM6 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 506H COM7 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 LED 1 8 duty LED_C1 8 LED_S1 8 Address 7 6 5 4 3 2 1 0 500H COM1 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 501H COM2 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 502H COM3 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 503H COM4 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 504H COM5 SEG8 SE...

Page 82: ...x enable 0 PWM01x x A B C output disable shared as I O 1 PWM01x output enable 2 0 PWM0COE PWM0BOE PWM0AOE 12 bit PWM output PWM0x enable 0 PWM0x x A B C output disable shared as I O 1 PWM0x output enable PWM output will be disabled at the same time when the PWM Enable register is clear to 0 The main purpose of the FLT pin is to inactivate the PWM output signals and driver them into an inactive sta...

Page 83: ...source select bit Combination control with TnCK0 1 0 Refer to TnCK0 1 0 4 FLTS FLT states bit 0 PWM is normal states cleared by software 1 PWM is in inactive states set automatically by hardware 3 FLTC FLT pin configuration 0 inactivate the PWM output when FLT is low level 1 inactivate the PWM output when FLT is high level 2 PWM0S PWM0 output normal mode of duty cycle 0 high active PWM0 output hig...

Page 84: ... x A B C output low When PP0 11 PP0 0 000H If PWM0S 1 regardless of the PWM duty cycle PWM0x x A B C output high Table 8 18 PWM Duty Control Register PWM0DL D5H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM0DL PD0 7 PD0 6 PD0 5 PD0 4 PD0 3 PD0 2 PD0 1 PD0 0 R W R W R W R W R W R W R W R W R W Reset Value POR WDT LVR PIN 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7 0 PD0 7 0 12 bit PWM duty ...

Page 85: ...alue will take effect in the next period 6 Change the data in PWMLO register not equal to 55h in order to enhance the anti noise ability PWM0 clock tPWM 01 02 03 04 05 06 07 08 09 0A 0B 0C0D0E 0F 01 02 03 04 05 06 07 08 09 0A 0B 0C0D 01 02 03 04 05 06 07 08 Write PPn 11 PPn 0 0DH Write PDn 11 PDn 0 07H PWM0 output PWMnS 0 Period cycle 0FH x tPWM Duty cycle 06H x tPWM Period cycle 0DH x tPWM Duty c...

Page 86: ...ad time enable PWM output Finally change the data in PWMLO not equal to 55H in order to make sure the PWM registers would not be changed by noise 2 In order to generate dead time please make sure that PWM0x Period PWM0x Duty 2 X PWM01x dead time control Otherwise the output of PWM01x is high level when PWMS 1 or GND when PWMS 0 3 PWMDT is to used to control Dead Time the step value is fixed oscill...

Page 87: ... LVR PIN 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7 PWM1EN PWM1 module enable control bit 0 disable PWM1 module 1 enable PWM1 module 6 PWM1S PWM1 output normal mode of duty cycle 0 high active PWM1 output high during duty time output low during remain period time 1 low active PWM1 output low during duty time output high during remain period time 5 4 TnCK1 1 0 PWM1 clock select bit 00 syst...

Page 88: ... Bit4 Bit3 Bit2 Bit1 Bit0 PWM1D PWM1D 7 PWM1D 6 PWM1D 5 PWM1D 4 PWM1D 3 PWM1D 2 PWM1D 1 PWM1D 0 R W R W R W R W R W R W R W R W R W Reset Value POR WDT LVR PIN 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7 0 PWM1D 7 0 PWM1 Duty control bit Special Case 1 When PWM1P PWM1D If PWM1S 0 PWM1 output high level If PWM1S 1 PWM1 output low level 2 WhenPWM1D 00H If PWM1S 0 PWM1 output low level If P...

Page 89: ... tPWM PWM1P F0H PWM1D 7FH PWM1 Output Example PWM1 clock tPWM 01 02 03 04 05 06 07 08 09 0A 0B0C0D0E 0F 01 02 03 04 05 06 07 08 090A 0B 0C0D 01 02 03 04 05 06 07 08 Write PWM1P 0DH Write PWM1D 07H PWM1 output PWM1S 0 Period cycle 0FH x tPWM Duty cycle 06H x tPWM Period cycle 0DH x tPWM Duty cycle 06H x tPWM Duty cycle 07H x tPWM PWM1 Output Period or Duty Cycle Changing Example ...

Page 90: ...erflow rate 16 or 32 10 bits 1 1 None 1 0 2 Asynch fSYS 32 or 64 11 bits 1 1 0 1 1 1 3 Asynch Timer 4 or 2 overflow rate 16 or 32 11 bits 1 1 0 1 Mode0 Synchronous Mode Half duplex This mode provides synchronous communication with external devices In this mode serial data is transmitted and received on the RXD pin TXD is used to output the shift clock The TXD clock is provided by the 3283 whether ...

Page 91: ... into the receive shift register the RX control block will deactivates RECEIVE and sets RI at the rising edge of the next system clock and the reception will not be enabled till the RI is cleared by software RxD D0 D1 D2 D3 D4 D5 D6 D7 RI Receive Timing of Mode 0 TxD Mode1 8 Bit EUART Variable Baud Rate Asynchronous Full Duplex This mode provides the 10 bits full duplex asynchronous communication ...

Page 92: ... RXD pin The divide by 16 counter divides each bit time into 16 states The bit detector samples the value of RXD at the 7th 8 th and 9 th counter states of each bit time At least 2 the sampling values have no difference in the state of the three samples data can be received This is done for noise rejection If the first bit after the falling edge of RXD pin is not 0 which indicates an invalid start...

Page 93: ...elow SERIAL CONTROLLER TX CLOCK TX START TX SHIFT TI RI RX CLOCK LOAD SBUF RX START RX SHIFT TXD Serial Port Interrupt PARIN LOAD CLOCK SOUT CLOCK SIN PAROUT RXD Read SBUF Internal Data Bus Receive Shift Register Internal Data Bus 32 32 1 TO 0 DETECTOR Write to SBUF BIT DETECTOR D8 SBUF RB8 Transmit Shift Register STOP START SAMPLE 1 0 2 D8 TB8 SMOD System Clock Transmission begins with a write to...

Page 94: ...cted and shifted into the shift register After shifting in 9 data bits and the stop bit the SBUF and RB8 are loaded and RI is set if the following conditions are met 1 RI must be 0 2 Either SM2 0 or the received 9th bit 1 and the received byte accords with Given Address If these conditions are met then the 9th bit goes to RB8 the 8 data bits go into SBUF and RI is set Otherwise the received frame ...

Page 95: ...es that will be coming After having received a complete message the slave sets SM2 again The slaves that were not addressed keep their SM2 setting and go on with their business ignoring the incoming data bytes Note In Mode0 SM2 is used to select baud rate doubling In Mode1 SM2 can be used to check the validity of the stop bit If SM2 1 the receive interrupt will not be activated unless a valid stop...

Page 96: ...th the 80C51 microcontrollers that do not support automatic address recognition So the user may implement multiprocessor communication by software recognition address according to the above mentioned method Frame Error Detection Frame error detection is available when the SSTAT bit in register PCON is set to logic 1 All the 3 error falg bits should be cleared by software after they are set even wh...

Page 97: ... runs at 1 4 of the system clock Mode1 and Mode3 In Mode1 Mode3 the baud rate can be fine adjusted The Mode1 3 baud rate equations are shown below BFINE SBRT F BaudRate 32768 16 sys For example Fsys 8MHz to get 115200Hz baud rate computing method of SBRT and SFINE as shown below 8000000 16 115200 4 34 SBRT 32768 4 32764 115200 8000000 16 X 4 BFINE BFINE 5 4 5 This fine tuning method to calculate t...

Page 98: ...t validation check any stop bit will set RI to generate interrupt In Mode2 3 any byte will set RI to generate interrupt 1 In Mode0 baud rate is 1 4 of system clock In Mode1 Enable stop bit validation check only valid stop bit 1 will set RI to generate interrupt In Mode2 3 only address byte 9th bit 1 will set RI to generate interrupt 5 TXCOL EUART0 Transmit Collision flag when TXCOL bit is read SST...

Page 99: ...led if using time4 as baud rate generator Fit EUART0 set SMOD in Mode2 the baud rate of EUART is doubled Both fit EUART0 and EUART0 6 SSTAT SCON 7 5 function select bit 0 SCON 7 5 operates as SM0 SM1 SM2 1 SCON 7 5 operates as FE RXOV TXCOL 5 SSTAT1 SCON1 7 5 function select bit 0 SCON1 7 5 operates as SM10 SM11 SM12 1 SCON1 7 5 operates as FE1 RXOV1 TXCOL1 3 0 Other See Power Management chapter T...

Page 100: ...validation check any stop bit will set RI to generate interrupt In Mode2 3 any byte will set RI to generate interrupt 1 In Mode0 baud rate is 1 4 of system clock In Mode1 Enable stop bit validation check only valid stop bit 1 will set RI to generate interrupt In Mode2 3 only address byte 9th bit 1 will set RI to generate interrupt 5 TXCOL1 EUART1 Transmit Collision flag when TXCOL1 bit is read SST...

Page 101: ... 0 0 0 0 Bit Number Bit Mnemonic Description 7 0 SADDR1 7 0 SFR SADDR defines the EUART1 s slave address 7 0 SADEN1 7 0 SFR SADEN1 is a bit mask to determine which bits of SADDR1 are checked against a received address 0 Corresponding bit in SADDR1 is a don t care 1 Corresponding bit in SADDR1 is checked against a received address Table 8 31 EUART1 Baud rate generator register 9DH 9CH Bank1 Bit7 Bi...

Page 102: ...MISO pin is placed in a high impedance state when the SPI operates as a slave that is not selected SS high A static high level on the SS pin puts the MISO line of a slave in a high impedance state 3 SPI Serial Clock SCK This signal is used to synchronize the data movement both in and out of the devices through their MOSI and MISO lines It is driven by the master for eight clock cycles which allows...

Page 103: ...tion The following diagram shows a detailed structure of the SPI module Internal Bus Clock Divider 128 4 8 16 32 64 Clock Select Clock Logic SPI Control DIR MSTR CPHA CPOL SSDIS SPR2 SPR1 SPR0 SPEN SPIF MODF WCOL RXOV SPSTA Pin Control Logic MOSI MISO SCK SS M S FCLK PERIPH Recieve Data Register SPI Interrupt Request 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Recieve Register Transmit Register SPDAT 8 bit Bu...

Page 104: ...I master device initiates all data transfers on a SPI bus The SPI operates in master mode when the MSTR is set in SPCON register Only one master can initiate transmission 2 Transmit When in SPI master mode writing a byte of data to the SPI data register SPDAT will write to the transmit shift buffer If the transmit shift register already contains data the SPI master will generate a WCOL signal to i...

Page 105: ...IF bit in SPSTA register before another byte enters the receive shift register Else a RXOV signal will be set to indicate data over run occurs and the receive shift register keep the byte that SPIF was lastly set also the SPI slave will not receive any further data until SPIF was cleared A SPI slave cannot initiate transfers Data to be transferred to the master device is pre loaded into the shift ...

Page 106: ...e the first SCK edge and a falling edge on the SS pin is used to start the transmission The SS pin must be toggled high and then low between each byte transmitted So SSDIS bit is invalid when CPHA 0 SPEN Internal SCK CPOL 0 SCK CPOL 1 MOSI from Master bit6 MSB bit5 bit4 bit3 bit2 bit1 LSB MISO from Slave SCK Cycle Number 1 2 3 4 5 6 7 8 Capture Point bit6 MSB bit5 bit4 bit3 bit2 bit1 LSB to Slave ...

Page 107: ...n WCOL flag in the SPSTA is set when a write to the SPDAT register is done during a transmit sequence WCOL does not cause an interruption and the transfer continues uninterrupted The WCOL bit is cleared by software 3 Overrun Condition RXOV An overrun condition occurs when the master or slave tries to send several data bytes and the slave or master has not cleared the SPIF bit issuing from the prev...

Page 108: ... Configure the SPI as a Slave 1 Configure the SPI as a Master 5 CPHA Clock Phase 0 Data sampled on first edge of SCK period 1 Data sampled on second edge of SCK period 4 CPOL Clock Polarity 0 SCK line low in idle state 1 SCK line high in idle state 3 SSDIS SS Disable 0 Enable SS pin in both Master and Slave modes 1 Disable SS pin in both master and slave modes MODF interrupt request will not gener...

Page 109: ...on flag 0 Cleared by software to indicate write collision has be processed 1 Set by hardware to indicate that a collision has been detected 3 RXOV Receive Overrun 0 Cleared by software to indicate receive overrun has be processed 1 Set by hardware to indicate that a receive overrun has been detected Table 8 35 Serial Peripheral Data Register A3H Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPDAT ...

Page 110: ...interrupt will be generated The ADC integrates a digital compare function to compare the value of analog input and the digital value in the AD converter If this function is enabled set EC bit in ADCON register and ADC module is enabled set ADON bit in ADCON register When the corresponding digital value of analog input is larger than the compare value in register ADDH L the ADC interrupt will occur...

Page 111: ... the reference voltage connected to VDD 1 the reference voltage input from VREF pin 3 1 SCH 2 0 ADC channel Select bits Combination control with SCH3 0000 ADC channel AN0 0001 ADC channel AN1 0010 ADC channel AN2 0011 ADC channel AN3 0100 ADC channel AN4 0101 ADC channel AN5 0110 ADC channel AN6 0111 ADC channel AN7 1000 ADC channel AN8 11xx internal 1 25V Reference 0 GO DONE ADC status flag bit 0...

Page 112: ... R W R W R W R W R W R W R W R W Reset Value POR WDT LVR PIN 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7 5 TADC 2 0 ADC Clock Period Select bits 000 ADC Clock Period tAD 2 tSYS 001 ADC Clock Period tAD 4 tSYS 010 ADC Clock Period tAD 6 tSYS 011 ADC Clock Period tAD 8 tSYS 100 ADC Clock Period tAD 12 tSYS 101 ADC Clock Period tAD 16 tSYS 110 ADC Clock Period tAD 24 tSYS 111 ADC Clock Peri...

Page 113: ... 8 16µs 12 8 16 112µs 111 0 25 32 8µs 0111 8 8 64µs 12 8 64 160µs 111 0 25 32 8µs 1111 15 8 120µs 12 8 120 216µs 12MHz 000 0 083 2 0 166µs tAD 1µs Not recommended 100 0 083 12 1µs 0000 2 1 2µs 12 1 2 14µs 100 0 083 12 1µs 0111 8 1 8µs 12 1 8 20µs 100 0 083 12 1µs 1111 15 1 15µs 12 1 15 27µs 111 0 083 32 2 7µs 0000 2 2 7 5 4µs 12 2 7 5 4 37 8µs 111 0 083 32 2 7µs 0111 8 2 7 21 6µs 12 2 7 21 6 54µs ...

Page 114: ...r AD Conversion 1 Select the analog input channels and reference voltage 2 Enable the ADC module with the selected analog channel 3 Delay 10us 4 Set GO DONE 1 to start the AD conversion 5 Wait until GO DONE 0 or ADCIF 1 if the ADC interrupt is enabled the ADC interrupt will occur user need clear ADCIF by software 6 Acquire the converted data from ADDH ADDL 7 Repeat step 3 5 if another conversion i...

Page 115: ...it6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 BUZCON BCA2 BCA1 BCA0 BZEN R W R W R W R W R W Reset Value POR WDT LVR PIN 0 0 0 0 Bit Number Bit Mnemonic Description 3 1 BCA 2 0 Buzzer output carrier frequency control bits 000 system clock 8192 001 system clock 4096 010 system clock 2048 011 system clock 1024 100 system clock 512 101 system clock 32 110 system clock 16 111 system clock 8 0 BZEN Enable buzzer o...

Page 116: ...r B3H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LPDCON LPDEN LPDF LPDMD LPDIF LPDS3 LPDS2 LPDS1 LPDS0 R W R W R R W R W R W R W R W R W Reset Value POR WDT LVR PIN 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7 LPDEN LPD Enable bit 0 Disable lower power detection 1 Enable lower power detection 6 LPDF LPD status Flag bit 0 No LPD happened clear by hardware 1 LPD happened set by hardware 5 LPDM...

Page 117: ... timer TLVR is about 30µs 60µs The LVR circuit has the following feature when the LVR function is enabled t means the time of the supply voltage below VLVR Generates a system reset when VDD VLVR and t TLVR Cancels the system reset when VDD VLVR or VDD VLVR but t TLVR The LVR function is enabled by the code option It is typically used in AC line or large capacity battery applications where heavy lo...

Page 118: ...e 8 43 Reset Control Register B1H Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RSTSTAT WDOF PORF LVRF CLRF WDT 2 WDT 1 WDT 0 R W R W R W R W R W R W R W R W Reset Value POR 0 1 0 0 0 0 0 Reset Value WDT 1 u u u 0 0 0 Reset Value LVR u u 1 u 0 0 0 Reset Value PIN u u u 1 0 0 0 Bit Number Bit Mnemonic Description 7 WDOF Watch Dog Timer Overflow or OVL Reset Flag Set by hardware when WDT overflow or...

Page 119: ...h set to 1 the CRC interrupt will generated in CPU and the interrupt flag CRCIF will be cleared by software Normal CRC mode the time of CPU operating is not influenced by the CRC check operating but the time of CRC check is long and uncontrollable High speed CRC mode in order to improve the time of CRC check there is a way which makes CPU into IDLE mode the time of CRC check will be reduced and CR...

Page 120: ... W R W R W R W R W Reset Value POR WDT LVR PIN 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7 0 CRCD 15 0 CRC check data register CRC Check Code updated when CRC Check is completed Note 1 Need a initial value in CRC check data register before CRC enable 2 Cannot set CRCADR 3 0 bits and CRCDL CRCDH when CRC is operating 3 The last two bytes in the CRC check region is dropped out of CRC check...

Page 121: ...k used in Timer3 will be opened in Power Down mode In Power Down mode if WDT is enabled WDT block will keep on working When entering Power Down mode all the CPU status before entering will be preserved Such as PSW PC SFR RAM are all retained By two consecutive instructions setting SUSLO register as 0x55 and immediately followed by setting the PD bit in PCON register will make SH79F3283 enter Power...

Page 122: ...L Idle mode control bit 0 Cleared by hardware when an interrupt or reset occurs 1 Set by software to activate the Idle mode Table 8 47 Suspend Mode Control Register 8EH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SUSLO SUSLO 7 SUSLO 6 SUSLO 5 SUSLO 4 SUSLO 3 SUSLO 2 SUSLO 1 SUSLO 0 R W R W R W R W R W R W R W R W R W Reset Value POR WDT LVR PIN 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7 0 S...

Page 123: ...llating in the following conditions Power on reset Pin reset LVR reset Watchdog Reset and Wake up from low power consumption mode After power on SH79F3283 will start power warm up procedure first and then oscillator warm up procedure Begin to run the program after the overflow Power Warm up Time Power On Reset Pin Reset Low Voltage Reset WDT Reset Not in Power Down Mode WDT Reset Wakeup from Power...

Page 124: ...8M RC 0110 Oscillator1 is internal 128k RC oscillator2 is 2M 12M crystal ceramic oscillator 1010 Oscillator1 is 32 768k crystal oscillator oscillator2 is internal 12M RC 1011 Oscillator1 is 32 768k crystal oscillator oscillator2 is internal 8M RC 1101 Oscillator1 is 32 768k crystal oscillator oscillator2 is 2M 12M crystal ceramic oscillator 1110 Oscillator1 is 2M 12M crystal ceramic oscillator osc...

Page 125: ...OP_P37 P34 0 port3 7 4 sink ability large mode default 1 port3 7 4 sink ability normal mode OP_MODSW 0 when MODSW 1 LCD LED count timer continue work 1 when MODSW 1 LCD LED count timer stop work keep the common value when LCD LED enable again continue scan present Common OP_OSCRFB 00 set OSC feedback resister is 2M 01 set OSC feedback resister is 1M 10 set OSC feedback resister is 500K default 10 ...

Page 126: ... SUBB A Rn Subtract register from A with borrow 0x98 0x9F 1 1 SUBB A direct Subtract direct byte from A with borrow 0x95 2 2 SUBB A Ri Subtract indirect RAM from A with borrow 0x96 0x97 1 2 SUBB A data Subtract immediate data from A with borrow 0x94 2 2 INC A Increment accumulator 0x04 1 1 INC Rn Increment register 0x08 0x0F 1 2 INC direct Increment direct byte 0x05 2 3 INC Ri Increment indirect R...

Page 127: ... 2 ORL direct A OR accumulator to direct byte 0x42 2 3 ORL direct data OR immediate data to direct byte 0x43 3 3 XRL A Rn Exclusive OR register to accumulator 0x68 0x6F 1 1 XRL A direct Exclusive OR direct byte to accumulator 0x65 2 2 XRL A Ri Exclusive OR indirect RAM to accumulator 0x66 0x67 1 2 XRL A data Exclusive OR immediate data to accumulator 0x64 2 2 XRL direct A Exclusive OR accumulator ...

Page 128: ... 2 ORL direct A OR accumulator to direct byte 0x42 2 3 ORL direct data OR immediate data to direct byte 0x43 3 3 XRL A Rn Exclusive OR register to accumulator 0x68 0x6F 1 1 XRL A direct Exclusive OR direct byte to accumulator 0x65 2 2 XRL A Ri Exclusive OR indirect RAM to accumulator 0x66 0x67 1 2 XRL A data Exclusive OR immediate data to accumulator 0x64 2 2 XRL direct A Exclusive OR accumulator ...

Page 129: ...OV Ri A Move accumulator to indirect RAM 0xF6 0xF7 1 2 MOV Ri direct Move direct byte to indirect RAM 0xA6 0xA7 2 3 MOV Ri data Move immediate data to indirect RAM 0x76 0x77 2 2 MOV DPTR data16 Load data pointer with a 16 bit constant 0x90 3 3 MOVC A A DPTR Move code byte relative to DPTR to A 0x93 1 7 MOVC A A PC Move code byte relative to PC to A 0x83 1 8 MOVX A Ri Move external RAM 8 bit addres...

Page 130: ...k Jump if carry flag is not set 0x50 2 2 4 JB bit rel not taken t k Jump if direct bit is set 0x20 3 4 6 JNB bit rel not taken taken Jump if direct bit is not set 0x30 3 4 6 JBC bit rel not taken taken Jump if direct bit is set and clear bit 0x10 3 4 6 CJNE A direct rel not taken taken Compare direct byte to A and jump if not equal 0xB5 3 4 6 CJNE A data rel not taken taken Compare immediate to A ...

Page 131: ... 0xD2 2 3 CPL C Complement carry flag 0xB3 1 1 CPL bit Complement direct bit 0xB2 2 3 ANL C bit AND direct bit to carry flag 0x82 2 2 ANL C bit AND complement of direct bit to carry 0xB0 2 2 ORL C bit OR direct bit to carry flag 0x72 2 2 ORL C bit OR complement of direct bit to carry 0xA0 2 2 MOV C bit Move direct bit to carry flag 0xA2 2 2 MOV bit C Move carry flag to direct bit 0x92 2 3 ...

Page 132: ...nstruction WDT on all other function block off IOP2 25 35 µA fOSC 128kHz OSCX off VDD 5 0V All output pins unload including all digital input pins unfloating CPU on execute NOP instruction LVR off WDT off all other function block off Stand by Current IDLE ISB1 3 5 mA fOSC 12MHz VDD 5 0V All output pins unload CPU off IDLE all digital input pins unfloating LVR on WDT off LCD on all other function b...

Page 133: ...ort drive ability large mode Code Option Output High Voltage 3 VOH3 VDD 0 7 V I O Ports P1 IOH 10mA VDD 5 0V Select Port1 drive ability normal mode Code Option Output High Voltage 4 VOH4 VDD 0 7 V I O Ports P1 IOH 18mA VDD 5 0V Select Port1 drive ability large mode Code Option Output Low Voltage1 VOL1 GND 0 6 V I O Ports P0 P1 P2 P4 P5 IOL 15mA VDD 5 0V Output Low Voltage2 VOL2 GND 0 6 V I O Ports...

Page 134: ...rror EZ 0 5 8 LSB fOSC 12MHz VDD 5 0V Total Absolute error EAD LSB fOSC 12MHz VDD 5 0V Total Conversion time TCON 16 tAD 12 bit Resolution VDD 5 0V tAD 1µs Internal reference VADREF 1 225 1 25 1 275 V 2 TA 25 C Note 1 Here the A D input Resistor is the DC input resistance of A D itself 2 Recommendations ADC connected signal source resistance of less than10kΩ AC Electrical Characteristics VDD 2 0V ...

Page 135: ...DD 2 0V 5 5V LVR Voltage3 VLVR3 2 7 2 8 2 9 V LVR Enable VDD 2 0V 5 5V LVR Voltage4 VLVR4 2 0 2 1 2 2 V LVR Enable VDD 2 0V 5 5V LVR Schmidt trigger VSMTLV 50 mV Drop Down Pulse Width for LVR TLVR 60 µs 12MHz Crystal Electrical Characteristics Parameter Symbol Min Typ Max Unit Condition Frequency F12M 12 MHz Capacitor CL 12 5 pF 32 768kHz crystal Electrical Characteristics Parameter Symbol Min Typ...

Page 136: ...SH79F3283 136 11 Ordering Information Part No Package SH79F3283P 032PR LQFP32 SH79F3283P 044PR LQFP44 SH79F3283U 048UR TQFP48 ...

Page 137: ...ules R Tray 032 pin 32 044 pin 44 048 pin 48 Dividing line SH 79 F 32 83 P 032 P R P LQFP package U TQFP package 83 Product serial number 32 Flash size 32K bytes F Flash Product 79 8051 core SH SinoWealth P LQFP package U TQFP package ...

Page 138: ...A1 0 002 0 006 0 05 0 15 A2 0 035 0 041 0 9 1 05 D 0 270 0 281 6 85 7 15 E 0 270 0 281 6 85 7 15 HD 0 346 0 362 8 8 9 2 HE 0 346 0 362 8 8 9 2 b 0 005 0 011 0 15 0 27 e 0 020 TYP 0 500 TYP c 0 004 0 008 0 090 0 200 L 0 018 0 030 0 45 0 75 L1 0 033 0 045 0 85 1 15 θ2 0 10 0 10 Notice 1 Both package length and width do not include mold flash 2 Tolerance is 0 1mm if not specified 3 Coplanarity 0 1mm ...

Page 139: ... 065 1 45 1 65 A1 0 000 0 001 0 01 0 21 A2 0 051 0 059 1 3 1 5 D 0 388 0 400 9 85 10 15 E 0 388 0 400 9 85 10 15 HD 0 465 0 480 11 8 12 2 HE 0 465 0 480 11 8 12 2 b 0 010 0 018 0 25 0 45 e 0 031 TYP 0 8 TYP c 0 004 0 008 0 09 0 20 L 0 017 0 031 0 42 0 78 L1 0 037 0 045 0 95 1 15 θ2 0 10 0 10 Notice 1 Both package length and width do not include mold flash 2 Tolerance is 0 1mm if not specified 3 Co...

Page 140: ...00 0 008 0 01 0 21 A2 0 051 0 059 1 30 1 50 D 0 268 0 281 6 80 7 15 E 0 268 0 281 6 80 7 15 HD 0 346 0 362 8 80 9 20 HE 0 346 0 362 8 80 9 20 b 0 010 0 018 0 25 0 45 e 0 031 TYP 0 8TYP c 0 004 0 008 0 09 0 20 L 0 016 0 031 0 40 0 78 L1 0 035 0 043 0 90 1 10 θ2 0 10 0 10 Notice 1 Both package length and width do not include mold flash 2 Tolerance is 0 1mm if not specified 3 Coplanarity 0 1mm max 4 ...

Page 141: ...SH79F3283 141 14 Product SPEC Change Notice Version Content Date 2 0 Original Jun 2021 ...

Page 142: ...ar the Products are prohibited to be used in following fields such as military national defense nuclear energy medical treatment and others that may cause personal injury death or environmental damage Users shall take all actions to ensure that the Products are used and sold in accordance with applicable laws and regulations The failure or malfunction of semiconductor products may occur Users of t...

Page 143: ... 31 7 5 3 Description 31 7 5 4 Register 31 7 5 5 Oscillator Type 33 7 5 6 Capacitor Selection for Oscillator 34 7 6 SYSTEM CLOCK MONITOR SCM 35 7 7 I O PORT 36 7 7 1 Features 36 7 7 2 Register 36 7 7 3 Port Diagram 38 7 7 4 Port Share 38 7 8 TIMER 44 7 8 1 Features 44 7 8 2 Timer2 44 7 8 3 Timer3 50 7 8 4 Timer4 52 7 8 5 Timer5 55 7 9 INTERRUPT 57 7 9 1 Feature 57 7 9 2 Interrupt Enable Control 57...

Page 144: ...rupts 107 8 6 9 Registers 108 8 7 ANALOG DIGITAL CONVERTER ADC 110 8 7 1 Feature 110 8 7 2 ADC Diagram 110 8 7 3 Register 111 8 8 BUZZER 115 8 8 1 Feature 115 8 8 2 Register 115 8 9 LOW POWER DETECT LPD 116 8 9 1 Feature 116 8 9 2 Register 116 8 10 LOW VOLTAGE RESET LVR 117 8 10 1 Feature 117 8 11 WATCHDOG TIMER WDT AND RESET STATE 118 8 11 1 Feature 118 8 11 2 Register 118 8 12 CRC VERIFICATION M...

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