SH79F3283
54
Registers
Table 7.34
Timer4 Control Register
C8H, Bank1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
T4CON
TF4
TC4
T4PS1
T4PS0
T4M1
T4M0
TR4
T4CLKS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
(POR/WDT/LVR/PIN)
0
0
0
0
0
0
0
0
Bit Number
Bit Mnemonic
Description
7
TF4
Timer4 overflow flag bit
0: No overflow (cleared by hardware)
1: Overflow (Set by hardware)
6
TC4
Compare function Enable bit
When T4M[1:0] = 00
0: Disable compare function of Timer4
1: Enable compare function of Timer4
When T4M[1:0] = 10 or 11
0: Timer4 can’t be re-trigged
1: Timer4 can be re-trigged
5-4
T4PS[1:0]
Timer4 input clock Prescale Select bits
00: 1/1
01: 1/8
10: 1/64
11: 1/256
3-2
T4M[1:0]
Timer4 Mode Select bit
00: Mode0, 16-bit auto-reload timer
01: Mode1, baud-rate generator for EUART
10: Mode2 with rising edge trig from pin T4 (system clock only, T4CLKS is invalid)
11: Mode2 with falling edge trig from pin T4 (system clock only, T4CLKS is invalid)
1
TR4
Timer4 start/stop control bit
0: Stop Timer4
1: Start Timer4
0
T4CLKS
Timer4 Clock Source select bit
0: System clock, T4 pin is used as I/O port
1: External clock from pin T4 (On the falling edge), the internal pull-up resister is
turned on
Table 7.35
Timer4 Reload/Counter Data Registers
CCH-CDH, Bank1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TL4
TL4.7
TL4.6
TL4.5
TL4.4
TL4.3
TL4.2
TL4.1
TL4.0
TH4
TH4.7
TH4.6
TH4.5
TH4.4
TH4.3
TH4.2
TH4.1
TH4.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
(POR/WDT/LVR/PIN)
0
0
0
0
0
0
0
0
Bit Number
Bit Mnemonic
Description
7-0
TL4.x
Timer4 Low & High byte counter, x = 0 - 7
TH4.x
