Sino Wealth SH79F3283, Manual

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SH79F3283
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7.9.5 Interrupt Vector
When an interrupt occurs, the program counter is pushed onto the stack and the corresponding interrupt vector address is
loaded into the program counter. The interrupt vector addresses are listed in
Interrupt Summary table .
7.9.6 Interrupt Priority
Each interrupt source can be individually programmed to one of four priority levels by setting or clearing corresponding bits in
the interrupt priority control registers IPL0, IPH0, IPL1, and IPH1. The interrupt priority service is described below.
An interrupt service routine in progress can be interrupted by a higher priority interrupt, but can not by another interrupt with
the same or lower priority.
The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority
levels are received simultaneously, the request of higher priority level is serviced.
If the same priority interrupt source apply for the interrupt at the beginning of the instruction cycle at the same time, an internal
polling sequence determines which request is serviced.
Interrupt Priority
Priority bits
Interrupt Lever Priority
IPHx IPLx
0 0 Level 0 (lowest priority)
0 1 Level 1
1 0 Level 2
1 1 Level 3 (highest priority)
Table 7.46 Interrupt Priority Control Registers
B8H, B4H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IPL0 - PADCL PT2L PS0L - PX1L PT5L PX0L
IPH0 - PADCH PT2H PS0H - PX1H PT5H PX0H
R/W - R/W R/W R/W - R/W R/W R/W
Reset Value
(POR/WDT/LVR/PIN)
- 0 0 0 - 0 0 0
B9H, B5H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IPL1 PSCML PT4L PPWML PT3S1L PX4L PX3L PX2L PSPIL
IPH1 PSCMH PT4H PPWMH PT3S1H PX4H PX3H PX2H PSPIH
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value
(POR/WDT/LVR/PIN)
0 0 0 0 0 0 0 0
Bit Number Bit Mnemonic Description
7-0 PxxxL/H Corresponding interrupt source xxx’s priority level selection bits