Silicon Laboratories Si8410, Manual, Page: 10 / 38

S i 8 4 1 0 / 2 0 / 2 1 ( 5 k V )
S i 8 4 2 2 / 2 3 ( 2 . 5 & 5 k V )
10 Rev. 1.1
100 Mbps Supply Current (All inputs = 50 MHz square wave, C
L
= 15 pF on all outputs)
Si8410Bx
V
DD1
V
DD2
—
— 2.0
3.6 3.0
4.5 mA
Si8420Bx
V
DD1
V
DD2
—
— 4.5
7.0 5.3
8.8 mA
Si8421Bx
V
DD1
V
DD2
—
— 5.3
5.3 6.6
6.6 mA
Si8422Bx
V
DD1
V
DD2
—
— 5.3
5.3 6.6
6.6 mA
Si8423Bx
V
DD1
V
DD2
—
— 3.4
6.6 5.1
8.3 mA
Timing Characteristics
Si8422Ax, Si8423Ax
Maximum Data Rate 0 — 1.0 Mbps
Minimum Pulse Width — — 250 ns
Propagation Delay t
PHL
, t
PLH
See Figure 1 — — 35 ns
Pulse Width Distortion
|t
PLH
– t
PHL
|
PWD See Figure 1 — — 25 ns
Propagation Delay Skew
2
t
PSK(P-P)
— — 40 ns
Channel-Channel Skew t
PSK
— — 35 ns
Si8422Bx, Si8423Bx
Maximum Data Rate 0 — 150 Mbps
Minimum Pulse Width — — 6.0 ns
Propagation Delay t
PHL
, t
PLH
See Figure 1 4.0 8.0 11 ns
Pulse Width Distortion
|t
PLH
– t
PHL
|
PWD See Figure 1 — 1.5 3.0 ns
Propagation Delay Skew
2
t
PSK(P-P)
— 2.0 3.0 ns
Channel-Channel Skew t
PSK
— 0.5 1.5 ns
Table 2. Electrical Characteristics (Continued)
(V
DD1
= 3.3 V ±10%, V
DD2
= 3.3 V ±10%, T
A
= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50

, ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. t
PSK(P-P)
is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.