Si3454-KIT
Confidential Rev. 0.1
17
7. Board Schematics, BOM, and Layout
The following are general PCB layout considerations. Detailed schematics, BOM, and layout can also be found in
the following sections. Visit the Silicon Labs Technical Support web page and register to submit a technical support
request, particularly if you are not closely following the recommended reference design.
7.1. Design and Layout Considerations
The Si3454 directly drives and senses detection and classification stimulus voltages. PoE power is enabled
through external FETs. PoE power supply currents in each channel are sensed using current shunt resistors with
sensed voltage referenced to GND.
Normally the layout will be 4-layer, with dedicated VPWR and GND planes for PoE power delivery. The ground
power plane does not generally have a high frequency content; so, it is acceptable to use a single GND plane and
tie GND, AGND, DGND pins to it. The thermal pad of the Si3454 is connected to GND. Si3454 internal dissipation
is modest, but for best performance the layout should include a thermal bond consisting of multiple vias between
the thermal pad and GND. The PoE power MOSFETs carry up to 800 mA dc and up to 5 A in faults; so, a 20 mil
trace with wide or multiple vias is also recommended.
The Si3454 includes a buck type dc-dc converter controller function, which generates a raw ~4 V power rail VCAP.
The buck regulator is able to supply 200 mA; so, within a group of Si3454 devices, only one buck regulator is
required. The single buck regulator supplies low drop-out (LDO) regulators within individual Si3454 devices to
generate their VDD = 3.3 V. Each LDO supplies the 3.3 V requirements of its own Si3454. The Si3454 VDD LDO is
able to supply additional current for an external device, such as an isolator or low-power-management
microcontroller.
The Si3454 buck regulator is a potential EMI source. The power devices, e.g. switching MOSFET, inductor, diode
and output capacitor should be located as close together as possible to minimize loop area. The entire switching
circuit should be shielded from Si3454 port connections to minimize the chance of interference.
To improve sensing accuracy, the Si3454 provides Kelvin connections for the resistor low side sense. The SENSEx
signals are connected to GND potential, but for best performance they should be routed separately from the GND
plane.
To avoid coupling between surge events and logic signals, it is recommended that VOUTn traces be well separated
from I
2
C interface pins.
A typical layer stackup is as follows:
1. Top: I
2
C, Si3454 Kelvin current sense
2. VPWR, VDD = 3.3 V
3. VEE = GND
4. Bottom: VOUT, switcher, VCAP
The I
2
C bus runs at 400 kHz maximum. The I
2
C bus lines should be routed away from analog lines like Rbias or
Vref but can otherwise be routed with ordinary care. If using a Silicon Labs I
2
C isolation product, please observe
the connections as per the reference design, which take into account required voltage margins and pullup values.
Summary of Contents for Si3454-KIT
Page 22: ...Si3454 KIT 22 Confidential Rev 0 1 Figure 21 Evaluation Board Top Side ...
Page 23: ...Si3454 KIT Confidential Rev 0 1 23 Figure 22 Evaluation Board Ground Layer ...
Page 24: ...Si3454 KIT 24 Confidential Rev 0 1 Figure 23 Evaluation Board Power Layer ...
Page 25: ...Si3454 KIT Confidential Rev 0 1 25 Figure 24 Evaluation Board Bottom Side ...
Page 35: ...Si3454 KIT Confidential Rev 0 1 35 Figure 32 Connector Board Bottom Side ...
