AN633
Rev. 0.7
19
7.5. Write and Read the FIFOs
There are two 64-byte FIFOs for RX and TX data in the Si4x6x.
To fill data into the transmit FIFO, the host MCU should pull the NSEL pin low and send the 0x66 Transmit FIFO
Write command ID followed by the bytes to be filled into the FIFO. Finally, the host MCU should pull the NSEL pin
high. Up to 64 bytes can be filled into the FIFO during one SPI transaction.
Figure 13. Transmit FIFO Write
If the host MCU needs to read the receive FIFO, it has to pull the NSEL pin low and send the 0x77 Receive FIFO
Read command ID. The MCU should provide as many clock pulses on the SCLK pin as necessary for the radio to
clock out the requested amount of bytes from the FIFO on the SDO pin. Finally, the host MCU should pull up the
NSEL pin.
Figure 14. Receive FIFO Read
If more than 64 bytes are written into the Transmit FIFO, then a FIFO overflow occurs. If more bytes are read from
the Receive FIFO than it holds, then FIFO underflow occurs. In either of these cases, the
FIFO_UNDERFLOW_OVERFLOW_ERROR interrupt flag will be set. The radio can also generate an interrupt on
the NIRQ pin if this flag is enabled. The interrupt flag has to be read, issuing a GET_CHIP_STATUS or
GET_INTERRUPT_STATUS command, to clear the pending interrupt and release the NIRQ pin.
0x66
Byt e 0
Byte n
NSEL
SDO
SDI
SCLK
0x77
NSEL
SD O
SDI
SCLK
Byte 0
Byte 1
Byte n
Summary of Contents for EZRADIOPRO Si4060
Page 24: ...AN633 24 Rev 0 7 Figure 20 Supply Current versus Time Diagram from Shutdown to RX State...
Page 67: ...AN633 Rev 0 7 67 Figure 48 Variable Length Packet Reception Flowchart...
Page 69: ...AN633 Rev 0 7 69 Figure 50 Packet Matching Reception Flowchart...
Page 73: ...AN633 Rev 0 7 73 Figure 54 Packet Reception with Automatic RX Hopping Flowchart...
Page 75: ...AN633 Rev 0 7 75 Figure 56 Packet Reception with Manual Rx Hopping...
Page 80: ...AN633 80 Rev 0 7 Figure 62 Long Packet Transmission Workflow...
Page 81: ...AN633 Rev 0 7 81 Figure 63 Long Packet RX Flowchart...
