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56
Rev. 0.7
10.4. Direct Reception (Synchronous and Asynchronous)
For legacy systems that perform packet handling within the host MCU or other baseband chip, it may not be
desirable to use the FIFO. The direct reception example code bypasses the RX FIFO entirely. The RX modulation
data is provided by an output pin of the RF chip to the host MCU. Data is not stored in the RX_FIFO after the
reception. In synchronous mode, the data and the clock signals are synchronized.
Figure 39. GPIO connections between the radio and the host MCU
Figure 40. Activate Direct Synchronous or Asynchronous Reception
Summary of Contents for EZRADIOPRO Si4060
Page 24: ...AN633 24 Rev 0 7 Figure 20 Supply Current versus Time Diagram from Shutdown to RX State...
Page 67: ...AN633 Rev 0 7 67 Figure 48 Variable Length Packet Reception Flowchart...
Page 69: ...AN633 Rev 0 7 69 Figure 50 Packet Matching Reception Flowchart...
Page 73: ...AN633 Rev 0 7 73 Figure 54 Packet Reception with Automatic RX Hopping Flowchart...
Page 75: ...AN633 Rev 0 7 75 Figure 56 Packet Reception with Manual Rx Hopping...
Page 80: ...AN633 80 Rev 0 7 Figure 62 Long Packet Transmission Workflow...
Page 81: ...AN633 Rev 0 7 81 Figure 63 Long Packet RX Flowchart...
