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Siemens SIMATIC IM 151/CPU, Manual

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Instruction List

B-4

ET 200S Interface Module IM 151/CPU

A5E00058783-01

Address Registers AR1 and AR2 (32 Bits)

The address registers contain the area-specific or general addresses for
instructions that use register-indirect addressing. The address registers are 32 bits
long.

The area-internal and/or area-crossing addresses have the following structure:

Area-internal address:

00000000 00000bbb bbbbbbbb bbbbbxxx

Area-crossing address:

10000yyy 00000bbb bbbbbbbb bbbbbxxx

Legend:

b

Byte address

x

Bit number

y

Area identifier (see Appendix B.4)

Status Word (16 Bits)

The status word bits are evaluated or set by the instructions.

The status word is 16 bits long.

Bit

Assign-

ment

Description

0

/FC

First check bit *

1

RLO

Result of (previous) logic operation

2

STA

Status *

3

OR

Or *

4

OS

Stored overflow

5

OV

Overflow

6

A0

Condition code

7

A1

Condition code

8

BR

Binary result

9 ...

15

Unassigned

–

*  Bit cannot be evaluated in the user program with the L STW instruction,
 

since it is not updated at program runtime.

Summary of Contents for SIMATIC IM 151/CPU

Page 1: ...ycle and Response Times 7 Getting Started 8 Configuration Frame and Parameter Assignment Frame for the ET 200S A Instruction List B Execution Times of the SFCs and SFBs C Migration of the IM 151 CPU D Glossary Index Edition 05 2000 A5E00058783 01 ET 200S Interface Module IM 151 CPU Manual This manual is part of the document package with the order number 6ES7 151 1AA00 8BA0 SIMATIC ...

Page 2: ...perated and maintained as recommended Trademarks SIMATIC SIMATIC HMI and SIMATIC NET are registered trademarks of SIEMENS AG Some of other designations used in these documents are also registered trademarks the owner s rights may be violated if they are used by third parties for their own purposes Safety Guidelines This manual contains notices which you should observe to ensure your own personal s...

Page 3: ...nfiguration engineers commissioning engineers and maintenance personnel who use the ET 200S with PLC functionality It consists of chapters containing instructions and reference chapters Delivery Package This delivery package order number 6ES7 151 1AA00 8BA0 consists of three manuals with contents as follows IM 151 CPU Interface Module Installing and wiring the ET 200S Commissioning and diagnostics...

Page 4: ...d I O system fulfills the requirements and criteria of IEC 1131 Part 2 and the requirements for obtaining the CE marking CSA UL and FM certifications have been obtained for the ET 200S Shipbuilding certification has been applied for You will find detailed information on these standards certificates and approvals in the ET 200S Distributed I O System manual Position in the Information Landscape In ...

Page 5: ...tents and lists of the figures and tables in the manual The sections of the chapters in the manual contain subheadings that allow you to gain a quick overview of the contents of the section You will find a glossary in the appendix at the end of the manual The glossary contains definitions of the main technical terms used in the manual At the end of the manual you will find a detailed index that en...

Page 6: ...Important Information vi ET 200S Interface Module IM 151 CPU A5E00058783 01 ...

Page 7: ...g the PROFIBUS Address 3 5 3 3 Network Components 3 7 3 4 Functions via the Programming Device OP 3 9 3 5 Direct Communication 3 10 4 Commissioning and Diagnostics 4 1 Configuring the IM 151 CPU 4 2 4 2 Resetting the Memory of the IM 151 CPU 4 4 4 3 Commissioning and Startup of the ET 200S 4 7 4 4 Diagnostics Using LEDs 4 9 4 5 Diagnostics via Diagnostic Address with STEP 7 4 11 4 6 Slave Diagnosi...

Page 8: ... 7 9 8 Getting Started 8 1 Step 1 Installing the ET 200S IM 151 CPU and S7 300 8 4 8 2 Step 2 Wiring the ET 200S IM 151 CPU and S7 300 8 5 8 3 Step 3 Commissioning the ET 200S IM 151 CPU 8 6 8 4 Step 4 Configuring the IM 151 CPU for Stand Alone Operation 8 7 8 5 Step 5 Programming the IM 151 CPU 8 9 8 6 Step 6 Test Run 8 10 8 7 Step 7 Upgrading the IM 151 CPU and Commissioning the S7 300 8 11 8 8 ...

Page 9: ...tructions with Condition Code Bits B 19 B 12 Edge Triggered Instructions B 25 B 13 Setting Resetting Bit Addresses B 26 B 14 Instructions Directly Affecting the RLO B 27 B 15 Timer Instructions B 28 B 16 Counter Instructions B 29 B 17 Load Instructions B 30 B 18 Load Instructions for Timers and Counters B 32 B 19 Transfer Instructions B 33 B 20 Load and Transfer Instructions for Address Registers ...

Page 10: ...ons B 46 B 36 Complement Formation B 47 B 37 Block Call Instructions B 48 B 38 Block End Instructions B 49 B 39 Exchanging Data Blocks B 49 B 40 Jump Instructions B 50 B 41 Instructions for the Master Control Relay MCR B 52 C Execution Times of the SFCs and SFBs C 1 System Functions SFCs C 1 C 2 System Function Blocks SFBs C 3 D Migration of the IM 151 CPU D 1 Differences to Selected S7 300 CPUs D...

Page 11: ... Addresses for the DP Master and ET 200S 4 11 4 3 Format of the Slave Diagnostic Data 4 15 4 4 Structure of the Module Diagnosis 4 20 4 5 Structure of the Module Status 4 21 4 6 Structure of the Station Diagnosis 1 4 22 4 7 Structure of the Station Diagnosis 2 4 23 5 1 Mode selector 5 4 5 2 Principle Behind Forcing 5 7 5 3 Position of the Memory Card Slot for the MMC on the IM 151 CPU 5 9 5 4 Exam...

Page 12: ...ts of the IM 151 CPU 4 24 5 1 Attributes of the Device Database DDB File 5 2 5 2 Positions of the Mode Selector 5 4 5 3 LEDs for CPU Functionality 5 5 5 4 Available MMCs 5 8 5 5 Firmware Update with MMC 5 10 5 6 Backing Up the Operating System 5 11 5 7 Features of the Clock 5 12 5 8 Overview of the Blocks 5 13 5 9 OBs for Cycle and Restart 5 14 5 10 OBs for Interrupts 5 14 5 11 OBs for Error Fault...

Page 13: ... for the Address Areas of the Intermediate Memory A 3 A 3 Structure of the Configuration Frame in the Normal Identifier Format AKF A 4 A 4 Structure of the Configuration Frame with Default Setting for the Address Areas Normal Identifier Format in Accordance with AKF A 5 D 1 Differences to Selected S7 300 CPUs D 2 D 2 Example Replacements under Options Rewire D 4 ...

Page 14: ...Contents xiv ET 200S Interface Module IM 151 CPU A5E00058783 01 ...

Page 15: ...provides information about The role of the IM 151 CPU interface module within the ET 200S distributed I O system Which manuals in the ET 200S manual package contain what information Chapter Overview In Section Contents Page 1 1 What Is the IM 151 CPU Interface Module 1 2 1 2 Guide to the ET 200S Manuals 1 5 1 ...

Page 16: ...sks An ET 200S with an IM 151 CPU can therefore exercise full and if necessary independent control over a process related functional unit and can be used as a stand alone CPU The use of the IM 151 CPU leads to further modularization and standardization of process related functional units and simple clear machine concepts How Is the IM 151 CPU Integrated in the ET 200S The IM 151 CPU interface modu...

Page 17: ...IM 151 CPU Interface module PM E power mo dule for electronic modules Electronic modules Power module for the PM D motor starter Direct on line starter Reversing starter TM E terminal modules for electronic modules Power bus Terminating module TM P terminal modules for power modules Figure 1 1 View of the ET 200S Distributed I O System with the IM 151 CPU ...

Page 18: ...llowing ET 200S faults SF Bus faults BF Supply voltage for electronic components ON Force requests FRCE Operating mode of the IM 151 CPU RUN and STOP Variants for connection to the PROFIBUS DP via RS485 and fiber optic cables FO variant How Is the ET 200S Configured with the IM 151 CPU To configure the ET 200S with the IM 151 CPU configuration and parameter assignment you require HWCONFIG which is...

Page 19: ...ed in the following manuals ET 200S Distributed I O System ET 200S Distributed I O System DS DS PM E 2DO 2AI 2AO PM E 2DO 2AI 2AO PM D IM 151 CPU IM 151 PM E 2DO 2AI 2AO IM 151 CPU ET 200S Distributed I O System IM 151 CPU Interface Module ET 200S Motor Starters Safety Integrated ET 200S SIGUARD Sy stem IM 151 CPU Interface Module Figure 1 2 Components and the Manuals Required for Them Where Do Yo...

Page 20: ...ics of the ET 200S x 6 Commissioning and diagnostics of the ET 200S with motor starters x 3 Commissioning and diagnostics of the ET 200S with the IM 151 CPU x 4 Functions of the IM 151 CPU x 5 General technical specifications of the ET 200S standards certificates and approvals EMC environmental conditions etc x 7 Technical specifications of interface modules terminal modules power and electronic m...

Page 21: ...ion Slot oriented address allocation is the default form of addressing in which STEP 7 allocates a fixed module base address to each slot number User oriented address allocation You can allocate each module any address within the available IM 151 CPU address area For information on the addressing of the IM 151 CPU on the PROFIBUS DP see Section 3 2 In This Chapter In Section Contents Page 2 1 Slot...

Page 22: ...xed and can be changed but there is a default address area 0 127 128 255 256 1279 1280 1535 1 byte per digital module or motor starter DP range 16 bytes per analog module Direct Communication Figure 2 1 Structure of the Default Address Area Slot Assignment The figure below shows an ET 200S configuration with digital electronic modules analog electronic modules process related modules and the slot ...

Page 23: ...wer modules 256 272 288 304 320 1248 The unassigned addresses in the range 64 to 127 are in the process image in default addressing and can be used any way you choose in the user program If 2 bits in a byte are already occupied by a digital module the remaining 6 bits cannot be used as you choose e g the bits 1 4 to 1 7 in Figure 2 3 You can use the bytes in the address areas that are not used by ...

Page 24: ...ss of the module on which all the addresses of the module depend 0 127 1535 Process image User Defined Addressing Figure 2 4 Structure of the Address Area for User Defined Addressing Note Bit specific addressing is not possible in user defined address allocation and compression of digital channels is therefore not supported It is not possible to compress addresses Advantages Advantages of user def...

Page 25: ...en user data is transferred between the IM 151 CPU and the DP master The intermediate memory consists of a maximum of 32 address areas Intermediate memory PROFIBUS DP ET 200S as DP slave DP master I O modules IM 151 CPU Data transfer between DP master and the ET 200S via an intermediate memory in the IM 151 CPU Data transfer between the IM 151 CPU and I O modules Figure 2 5 Principles of Data Tran...

Page 26: ...nfiguration Example 1 Example 2 Example 3 Example 4 Input address areas Bytes per address area 16 4 2 32 16 4 0 0 Output address areas Bytes per address area 16 4 2 32 16 2 32 2 Total no of address areas Total no of bytes for inputs Total no of bytes for outputs 32 64 64 4 64 64 32 64 32 32 0 64 Data consistency You define data consistency as byte word or overall consistency per address area Consi...

Page 27: ...ble via the process image 1 to 32 byte data consistency on the PROFIBUS DP with SFC 14 and SFC 15 If you want to access data in the intermediate memory you have to read the input data with SFC 14 DPRD_DAT and write the output data with SFC 15 DPWR_DAT These SFCs have data consistency of 1 to 32 bytes You can only copy the input data read with SFC 14 as a block of 1 to 32 bytes to a memory marker a...

Page 28: ...he IM 151 CPU is configured with STEP 7 for operation in the S5 or in non Siemens systems it is clear that only the logical addresses within the slave CPU are allocated The addresses are then assigned in the master system using the specific configuration tool of the master system Addressing Interface in STEP 7 The following table illustrates the principles of address allocation You will also find ...

Page 29: ... data unit consistency i e word 16 words of output data unit consistency i e word If the IM 151 CPU is configured for stand alone operation no DP operating mode there is no default setting for the address areas because an intermediate memory is not configured in stand alone operation Sample Program Below you will see a sample program for data interchange between the DP master and the DP slave You ...

Page 30: ...area as of address 300 12C hexadecimal with a length of 8 bytes as of memory byte 60 In the IM 151 CPU Receive data from the DP master stored in MB 30 to 37 CALL SFC 14 LADDR W 16 84 RET_VAL MW 20 RECORD P M30 0 Byte8 Call system function 14 Write the data from the input address area as of address 132 84 hexadecimal with a length of 8 bytes to memory byte 30 Postprocess received data L MB 30 L MB ...

Page 31: ...tion Chapter Overview In Section Contents Page 3 1 ET 200S in the PROFIBUS Network 3 2 3 2 Setting the PROFIBUS Address 3 5 3 3 Network Components 3 7 3 4 Functions via the Programming Device OP 3 9 3 5 Direct Communication 3 10 More Information You will find more information on the structure of networks in the manual for the DP master Connecting Fiber Optic Cables to the IM 151 CPU FO You can fin...

Page 32: ...The ET 200S can be configured and programmed from this programming device 2 PG OP 25 6 Operating and monitoring functions can be executed on the ET 200S ET 200X ET 200X Figure 3 1 Example of a PROFIBUS Network Hardware Prerequisites in the Programming Device OP for Accessing the ET 200S Before you can access an IM 151 CPU from a programming device operator panel the programming device operator pan...

Page 33: ... However you can still install OPs OSs operator panels operator stations as fixed components of the PROFIBUS network for operating and monitoring functions You cannot access an ET 200S from more than five devices in parallel 1 connection is reserved for the programming device 1 connection is reserved for an operator panel or an operator station 3 connections are available as desired for programmin...

Page 34: ...in the DP Master The programming device is connected to the ET 200S on a stand alone basis for commissioning you don t add the ET 200S to the PROFIBUS network until later Note A special setting must be made in STEP 7 for the stand alone operation of the ET 200S with the IM 151 CPU if there is no active PROFIBUS node on the bus except the programming device see Section 3 4 ET 200S PG Figure 3 3 The...

Page 35: ...ule Permissible PROFIBUS DP addresses are 1 to 125 If you set an invalid address the IM 151 CPU will not start up It can then be reached on the PROFIBUS bus system at address 126 Each address can be allocated only once on the PROFIBUS DP The PROFIBUS address configured in STEP 7 must be identical to the DIP switch setting If the setting does not match the IM 151 CPU will not start up It can then b...

Page 36: ...FF DP slave operation 64 32 16 8 4 2 1 ON OFF Example DP address 64 32 2 1 99 _______ Switchover from DP slave to stand alone operation IM 151 CPU Figure 3 4 Setting the PROFIBUS Address Changing the PROFIBUS DP You change the PROFIBUS DP address in exactly the same way you set it Any changes made to the PROFIBUS DP address are valid for the ET 200S after the interface module is powered up The PRO...

Page 37: ... can be dragged conditionally resistant to welding with PUR sheath To connect the programming device and the ET 200S on the PROFIBUS DP network Bus connector without a programming device socket up to 12 Mbps 6ES7 972 0BA10 0XA0 with a straight outgoing cable unit 6ES7 972 0BA40 0XA0 with a slanted outgoing cable unit To make a dual connection for the programming device and the DP master on the PRO...

Page 38: ... bus connector is described in the Product Information document for the bus connector S7 300 DP master ET 200S PG Programming device connecting cable Bus cable Bus connector with a programming device socket Connector Bus cable Figure 3 5 Connecting the DP Network Connecting the IM 151 CPU FO You can find information on the connection and wiring of fiber optic cables in the chapter on wiring and fi...

Page 39: ...connect an ET 200S to a programming device on a stand alone basis you must specify a setting for the programming device interface in STEP 7 for the execution of online functions on the IM 151 CPU e g downloading a configuration or user program to the IM 151 CPU or reading out information from the IM 151 CPU online Proceed as follows 1 In STEP 7 choose the Setting the PG PC Interface tool Start STE...

Page 40: ...eavesdropper recipient can directly access changes to the input data of remote DP slaves During configuration in STEP 7 you set via the relevant I O input addresses the address area of the recipient at which the required data of the sender is to be read Example Figure 3 6 gives you an example of the relationships you can configure in direct communication in STEP 7 V 5 1 with an IM 151 CPU Other DP...

Page 41: ...rect communication One pick up is possible per sender Note The system load increases with the number of configured recipients The total system load is specified as a multiplying factor for the run times of the individual statements Diagnostics in Direct Communication Only the results of connection monitoring can be used in the diagnostics of the DP slaves configured for direct communication becaus...

Page 42: ...ET 200S in the PROFIBUS Network 3 12 ET 200S Interface Module IM 151 CPU A5E00058783 01 ...

Page 43: ...igned to make handling and commissioning as simple as possible If a fault or an error should occur in spite of this you can analyze it using the LEDs the slave diagnosis and the diagnostic options in STEP 7 Interrupt Evaluation To help you evaluate the interrupts of the ET 200S we will examine the difference between these and the interrupts of the S7 M7 DP master and other DP masters Chapter Overv...

Page 44: ...figuration applies both to the variant with RS 485 and the variant with a fiber optic cable connection The first plug in modules can be configured as of slot 4 The following configuration options are available Table 4 1 Configuration Options Configuration Environment Configuration Tool Configurable Operating Mode SIMATIC S7 STEP 7 HWCONFIG as of V5 1 Stand alone IM 151 CPU as S7 slave SIMATIC S5 C...

Page 45: ...er station in the same project 3 Drag the ET 200S with the IM 151 CPU from the Hardware Catalog window from the configured stations container and drop it on the icon for the DP master system 4 Double click the intelligent DP slave icon and select the Interconnecting tab Specify on this tab which station is to represent the intelligent DP slave 5 Select the intelligent DP slave and click the Interc...

Page 46: ...th the Mode Selector Resetting the Memory with the Programming Device Described in this chapter Only possible during CPU STOP see the programming device manuals and the STEP 7 online help system Resetting the Memory of the IM 151 CPU with the Mode Selector To reset the memory of the IM 151 CPU using the mode selector proceed as follows see also Figure 4 1 1 Switch the mode selector to the STOP pos...

Page 47: ...t with the programming device see the STEP 7 user manual What Happens in the CPU Component of the IM 151 CPU Table 4 3 Internal CPU Events at Memory Resetting Event Response of the CPU in the IM 151 CPU Sequence of operations in the CPU component of the IM 151 CPU 1 The CPU deletes the entire user program in working memory and the load memory 2 The CPU deletes the backup memory retentive data 3 Th...

Page 48: ...058783 01 Note If the CPU cannot copy the contents of the memory module and requests a memory reset Remove the memory module Reset the CPU memory Read out the diagnostic buffer You can read out the diagnostic buffer with the programming device see the STEP 7 online help system ...

Page 49: ...m manual 3 Wire the ET 200S distributed I O system see the ET 200S Distributed I O System manual 4 During configuration as a DP slave specify in the configuration software the address areas in the IM 151 CPU via which data exchange with the DP master is to take place or use the ET 200S default setting see Section 2 4 5 Switch on the sensor supply voltage for the ET 200S 6 If necessary switch on th...

Page 50: ... downloaded from the programming device to the memory module inserted in the CPU by means of the Load User Program function Transfer by means of the memory module The user program is transferred to the memory module on the programming device The memory module is then inserted in the CPU and the memory reset request acknowledged See Section 5 4 Memory Module Tip Program OB 82 and 86 During Commissi...

Page 51: ...LED for indicating that the ET 200S is connected to a power supply FRCE LED comes on if a force request is active RUN LED for indicating that the CPU component of the IM 151 CPU is in RUN mode STOP LED for indicating that the CPU component of the IM 151 CPU is in STOP mode The meaning of the LEDs for CPU functionality is described in detail in Section 5 2 ON LED Is Off If the ON LED is off either ...

Page 52: ...tive LED flashes On Parameter assignment error there is no data exchange Slave not configured or incorrectly configured Incorrect but permissible station address set Configured address areas of the actual configuration not identical to the target configuration Station failure of a configured sender in direct data communication DP master does not exist is switched off but a connection to the progra...

Page 53: ... the SIMATIC S7 range on the PROFIBUS DP diagnostic addresses are assigned in STEP 7 as follows You specify two diagnostic addresses during configuration PROFIBUS ET 200S DP Master SIMATIC S7 Diagnostic address Diagnostic address When configuring the DP master you specify in the associated project for the DP master a diagnostic address for the ET 200S During configuration of the ET 200S STEP 7 set...

Page 54: ... CPU During I O access to the transfer area OB 122 is called I O access error OB 86 is called with the message Station failure incoming event diagnostic address of the IM 151 CPU During I O access to the transfer area OB 122 is called I O access error ET 200S RUN STOP OB 82 is called with the message Faulty module incoming event diagnostic address of the IM 151 CPU variable OB82_MDL_STOP 1 ET 200S...

Page 55: ...gnostic address not relevant The CPU calls OB 82 with the following information OB 82_MDL_ADDR 1022 OB82_EV_CLASS B 16 39 incoming event OB82_MDL_DEFECT Module fault Tip This information is available in the diagnostic buffer of the CPU In the user program you should also program SFC 13 DPNRM_DG to read out the slave diagnosis CPU in IM 151 CPU RUN STOP The CPU generates a diagnostic frame slave di...

Page 56: ...P master interrupts are appear in the station diagnosis of the IM 151 CPU see Section 4 6 6 You must continue processing the results of the diagnosis in the user program of the DP master Note Note the following in order to be able to evaluate the diagnostic interrupt and process interrupt via the station diagnosis when using a different DP master The DP master should be able to store diagnostic me...

Page 57: ...Module Diagnostics Byte x Station Diagnostics Byte x 1 to Byte y the length depends on the number of address areas configured for the intermediate memory1 the length depends on the type of interrupt 1 Exception If the DP master is incorrectly configured the DP slave interprets 35 configured address areas 46H in byte 6 Byte y 1 to Byte z the length depends on the number of configured address areas ...

Page 58: ...ve s actual configuration Was the software set for the right station type or the right DP slave configuration 3 1 Diagnostic interrupt generated by a RUN STOP transition on the CPU 0 Diagnostic interrupt generated by a STOP RUN transition on the CPU You can read out the diagnostic data 4 1 Function is not supported for instance changing the DP address at the software level Check the configuring da...

Page 59: ...is bit is always 1 when there is a DP slave with this DP address 3 1 The watchdog monitor has been activated for this DP slave 4 0 This bit is always 0 5 0 This bit is always 0 6 0 This bit is always 0 7 1 DP slave is deactivated that is to say it has been removed from the scan cycle Station Status 3 Table 4 9 Structure of Station Status 3 Byte 2 Bit Description 0 to 6 0 These bits are always 0 7 ...

Page 60: ...IBUS address diagnostic byte The master that parameterized the DP slave The master that has read and write access to the DP slave Master PROFIBUS Address Table 4 10 Structure of the Master PROFIBUS Address Byte 3 Bit Description 0 to 7 DP address of the DP master that parameterized the DP slave and has read write access to that DP slave FFH DP slave was not parameterized by a DP master ...

Page 61: ...1 4 6 3 Manufacturer ID Definition The manufacturer identification contains a code specifying the DP slave s type Manufacturer ID Table 4 11 Structure of the Manufacturer Identification Bytes 4 and 5 Byte 4 Byte 5 Manufacturer Identification for 80H 6CH IM 151 CPU 80H 6DH IM 151 CPU FO ...

Page 62: ... of the IM in STOP 0 Target actual configuration or CPU component of the IM in RUN Code for module diagnosis 0 1 7 6 5 4 1 3 1st configured address area Bit no Target configuration actual configuration Target configuration actual configuration 2nd configured address area 3rd configured address area 4th configured address area 5th configured address area 2 0 Bit no Byte 8 7 1 3 6 5 4 2 0 Byte 9 Byt...

Page 63: ...4 Bit no Modules 1 to 4 Byte x Modules 5 to 32 Byte x 12 Modules 33 to 35 00B Module o k valid user data Module 2 CPU CPU in RUN 01B Module o k invalid user data Module 2 CPU CPU in STOP 10B Incorrect module invalid user data 11B No module or module failure invalid user data Status type Module status not relevant 7 0 Bit no Code for the station diagnosis 0 0 6 Length of the module status including...

Page 64: ...tructure and contents of the bytes for the IM 151 CPU Byte y 2 01H Code for diagnostic interrupt 02H Code for process interrupt Byte y 5 Byte y 1 7 0 Bit no Length of the station diagnosis including byte y 1 8 bytes for the process interrupt and 20 bytes for the diagnostic interrupt Code for the station diagnosis 0 0 6 Byte y 3 Number of the configured address area in the intermediate memory Addit...

Page 65: ...ytes of the diagnostic data The next 12 bytes are always 0 For the process interrupt you can program four bytes of interrupt information You transfer these 4 bytes to the DP master in STEP 7 using SFC 7 DP_PRAL see Section 4 5 Diagnostic Data The figure below shows the structure and contents of the bytes for the diagnostic interrupt Bytes y 8 to y 20 are set to 0 Byte y 5 7 0 Bit no Byte y 6 Byte ...

Page 66: ...Extract Module identification W 16 xy11 CPU identification W 16 0111 CPU features W 16 xy12 All features Features of a group SSL sublist header information only W 16 0012 W 16 0112 W 16 0F12 User memory areas W 16 xy13 Records of all user memory areas W 16 0013 System areas W 16 xy14 Records of all system areas W 16 0014 Block types W 16 xy15 Records of all block types Records of all OBs W 16 0015...

Page 67: ...P station W 16 0A91 W 16 0C91 W 16 0D91 Mounting rack station status information W 16 xy92 Preset status in the central configuration of the master system Actual status in the central configuration of the master system OK status of the expansion units of the master system SSL sublist header information only W 16 0092 W 16 0292 W 16 0692 W 16 0F92 Diagnostic buffer W 16 xyA0 All the entries that ca...

Page 68: ...Commissioning and Diagnostics 4 26 ET 200S Interface Module IM 151 CPU A5E00058783 01 ...

Page 69: ...grated clock blocks for the user program and parameters that can be set Chapter Overview In Section Contents Page 5 1 Data for the PROFIBUS DP 5 2 5 2 The Mode Selector and LEDs 5 4 5 3 Force 5 6 5 4 Memory Module 5 8 5 5 Clock 5 12 5 6 Blocks 5 13 5 7 Parameters 5 16 5 8 Parameterization of the Reference Junction for the Connection of Thermocouples 5 18 5 8 Removal and Insertion of Modules During...

Page 70: ...eb site http www ad siemens de support html_00 index shtml http www ad siemens de csi gsd Alternatively you can obtain the DDB file via modem on 49 0 911 737972 or at CompuServe in AUTFORUM GO AUTFORUM Important Features If you do not have the DDB file to hand the following table lists the most important features of the IM 151 CPU Tabelle 5 1 Attributes of the Device Database DDB File Feature DP K...

Page 71: ...ssignment data User_Prm_Data Yes Minimum interval between two slave list rotations Min_Slave_Intervall 1 100 s Modular device Modular_Station 1 Maximum number of modules Max_Module 35 Maximum number of inputs in bytes Max_Input_Len 64 Maximum number of outputs in bytes Max_Output_Len 64 Maximum combined number of inputs and outputs in bytes Max_Data_Len 128 Central display of vendor specific statu...

Page 72: ...r in which they are arranged on the IM 151 CPU Table 5 2 Positions of the Mode Selector Position Description Description RUN P RUN PROGRAM mode The CPU processes the user program STOP STOP mode The CPU does not process the user program Programs can Be read out from the CPU using a programming device CPU PG Transferred to the CPU PG CPU MRES Reset CPU memory Momentary contact position of the mode s...

Page 73: ...startup of the CPU component the STOP LED also lights up when the STOP LED goes off the outputs are enabled Flashes at 0 5 Hz when the CPU has reached a breakpoint you have set At the same time the STOP LED comes on STOP yellow STOP mode Comes on when the CPU component Is not processing a user program Has reached a breakpoint you have set At the same time the RUN LED flashes at 0 5 Hz Flashes at 0...

Page 74: ...l as by I O read commands L PIW x for example in the user program or by PG OP write functions Outputs preset with force values only return the force value provided the user program does not execute any write accesses to the outputs using I O write commands e g T PQB x and provided no PG OP functions write to these outputs It is essential to note that force values in the process image input output ...

Page 75: ...access in your user program If for example an enable sensor f in your system is defective and it continually indicates a logical 0 to your user program for example via input 1 2 you can bridge this sensor by forcing the input to 1 ensuring that your system continues to operate However because the sensor is out of operation you must monitor the functionality by different means to avoid injury to th...

Page 76: ...th STEP 7 Data for a firmware update operating system Features The micro memory card has the following features Compact robust design Integrated write protection temporary and permanent Integrated error correction in the memory field Hot swapping is possible Fixed individual card identification Polarity reversal protection Micro Memory Cards that Can Be Used The following memory modules are availa...

Page 77: ...e card easily To eject the card you require a small screwdriver or ball point pen MEM 6ES7 953 8Lx00 0AA0 Micro Memory Card SIMATIC SIEMENS Ejector IM 151 CPU MMC Figure 5 3 Position of the Memory Card Slot for the MMC on the IM 151 CPU If a new MMC is inserted in the memory card slot the CPU of the module requests a memory reset Note The user program should be saved explicitly on the MMC The MMC ...

Page 78: ... blank MMC using STEP 7 and your programming device 2 Deenergize the IM 151 CPU and insert the MMC with the FW update 3 Switch the power on The IM 151 CPU automatically detects the MMC with the FW update and starts the FW update All the LEDs light up during the FW update except the FRCE LED The STOP LED flashes after the FW update has been completed In this way the IM 151 CPU requests a memory res...

Page 79: ...uests a memory reset 2 Hold the mode selector in the MRES position 3 Switch the power off then on and keep the mode selector in the MRES position until STOP RUN and FRCE LEDs start flashing 4 Move the mode selector to STOP 5 Move the mode selector briefly to MRES then let it snap back to STOP The IM 151 CPU starts to back up the operating system on the MMC All the LEDs light up during backup The S...

Page 80: ...erence Manual and Appendix C Features The table below indicates the features and functions of the clock When you parameterize the CPU in STEP 7 you can also set functions such as synchronization and correction factors refer to the STEP 7 online help system for information on how to do this Table 5 7 Features of the Clock Features IM 151 CPU Type Software clock Manufacturer setting DT 1994 01 01 00...

Page 81: ...formation You will find a detailed description of the blocks and the start events listed below in the System and Standard Functions Reference Manual There is an overview of all the STEP 7 documentation in the ET 200S Distributed I O System manual Overview of All the Blocks Table 5 8 Overview of the Blocks Block Number Area Maximum Size Remarks OB 13 8 KB All the possible OBs are listed below this ...

Page 82: ... Invoked OB Possible Start Events Time of day interrupt OB 10 Automatic start after setting and activation of the time of day interrupt using STEP 7 Activation via SFC 30 after setting with STEP 7 or SFC 28 Delay Interrupt OB 20 Expiration of the time specified in SFC32 Watchdog interrupt default 100 ms clock pulse OB 35 Depending on the clock pulse parameter assignment with STEP 7 Process interru...

Page 83: ...cause of event still exists Programming error OB 121 An event occurring due to an error in program scanning e g due to the call of a block not loaded in the CPU Error during direct access to I O OB 122 Error during read access Error during write access If OBs 80 85 86 121 are missing or with OB 85 and the corresponding start event the IM 151 CPU goes into STOP Points to Note About OB 122 Note Note...

Page 84: ...memory Yes no Memory byte 0 to 255 Startup characteri stics Automatic manual startup after power on Warm restart Monitoring time for Finished message by means of modules 100 ms Transfer of the parameters to modules 100 ms 1 to 65000 1 to 65000 Startup at preset configuration not equal to actual con figuration Yes no System diagno stics Report cause of STOP Yes no Retentivity Number of memory bytes...

Page 85: ...ach access For incoming and outgoing errors No call Protection Level of protection 1 Key switch 2 Write protection 3 Write read protection Mode Process mode permissible cycle increase ms from 3 to 65535 Test mode Module parame ters Number of reference junctions Activated Module number Channel number 8 Yes no From 5 to 66 0 1 Interference frequency suppression 50 Hz 60 Hz DP station address CPU DP ...

Page 86: ...he RTD module slot to the corresponding reference junction Channel number of reference junction 1 to channel number of reference junction 8 RTD on channel 0 RTD on channel 1 Example see Figure 5 4 You can use this parameter to define the channel 0 1 for reference temperature measurement determining the compensation value for the assigned RTD module slot RTD Module Parameter Range Explanation Measu...

Page 87: ...5 4 Example of a Parameterization Dialog Box for the CPU Module Data in STEP 7 V5 1 Reference You can find detailed information on the procedure the connection system and an example of parameterization in the chapter entitled Analog Electronic Modules in the ET 200S Distributed Device manual ...

Page 88: ...e of whether the power module is switched on or off If OB 83 is in the memory of the CPU the IM 151 CPU remains in RUN The absence of the module is noted in the system status list If the module that has been removed is accessed from the user program an I O access error occurs with a corresponding entry in the diagnostic buffer In addition OB 122 is called If OB 122 is in the memory of the CPU the ...

Page 89: ...is called with the corresponding diagnostic buffer entry event ID 3861H OB 83 is called with the corresponding diagnostic buffer entry event ID 3863H The CPU reparameterizes the module The CPU does not reparameterize the module If parameter assignment is successful the module is entered in the system status list as available The module remains entered in the system status list as unavailable The S...

Page 90: ...nactive for the process The inputs of digital modules and FM modules return 0 the inputs of analog modules return 7FFFH What Happens When Power Modules Are Switched On During Operation If the load power supply to a power module is switched on during operation the following activities take place If you enable diagnostics when assigning parameters for the power module the diagnostic interrupt OB 82 ...

Page 91: ...5E00058783 01 Technical Specifications In This Chapter In this chapter you will find The technical specifications of the IM 151 CPU interface module Chapter Overview In Section Contents Page 6 1 Technical Specifications of the IM 151 CPU 6 2 6 ...

Page 92: ... the PROFIBUS DP Stand alone operation possible 24 KB working memory not buffered 40 KB integrated load memory RAM not buffered Powerfail proof storage of the user program and configuration via the MMC memory module Programmable with STEP 7 as of V5 1 Speed approx 0 5 ms per 1000 binary instructions Maximum configuration of the local I Os 63 ET 200S modules General Technical Specifications The IM ...

Page 93: ...M 151 CPU 1 IM 151 CPU 2 1 3 RxD TxD P Data line B 1 2 6 7 4 RTS Request To Send 2 3 4 5 7 8 9 5 M5V2 Data reference potential from the station 5 6 P5V2 Supply Plus from the station RS 485 interface 7 RS 485 interface 8 RxD TxD N Data line A 9 Receiver IM 151 CPU FO only Fiber optic interface Sender 2L 1M 2M 1 L 1 L 24V DC 2L 1M 2M 1 L 2L 24 V DC to loop through 1M Chassis ground 2M Chassis ground...

Page 94: ...rface module Backplane bus Electronics FRCE BF SF RUN STOP Figure 6 1 Basic Circuit Diagram for the IM 151 CPU Basic Circuit Diagram for the IM 151 CPU FO L M Internal power supply PROFIBUS address ON CPU P ROM RAM Mode selector MRES RUN P STOP MMC PROFIBUS DP connection fiber optic cable Fiber op tic inter face A B A B ET 200S backplane bus interface module Backplane bus Electronics FRCE BF SF RU...

Page 95: ...retentivity from T 0 to T 127 Preset No retentive times Timing range 10 ms to 9990 s IEC Timers Yes Type SFB Data areas and their retentive characteristics Total retentive data area incl memory markers timers counters Max 4736 bytes Bit memories 256 bytes Adjustable retentivity MB 0 to MB 255 Preset retentivity MB 0 to MB 15 Clock memory 8 1 memory byte Data blocks max 127 DB 0 reserved Size max 8...

Page 96: ...GET S7 communication Yes server User data per job max 160 bytes Number of which consistent 32 bytes S7 compatible communication No Standard communication No Interface FO Type of interface Integrated RS 485 interface Fiber optic interface and Integrated RS 485 interface Physical system RS 485 FO or RS 485 Galvanically isolated Yes No Power supply to the interface 15 to 30 V DC Max 80 mA Number of c...

Page 97: ...C User program security Password protected Dimensions and Weight Installation dimensions W H D mm 60 x 119 5 x 75 Weight Approx 200 g Voltages Currents Power supply Rated value 24 V DC Permissible range 20 4 to 28 8 V Polarity reversal protection Yes Voltage failure buffering 20 ms Insulation tested at 500 V DC Current consumption from supply voltage 1L Approx 250 mA Power supply for the ET 200S b...

Page 98: ...Technical Specifications 6 8 ET 200S Interface Module IM 151 CPU A5E00058783 01 ...

Page 99: ...f your user program see the STEP 7 User Manual The response time is more important for the process In this chapter we will show you in detail how to calculate the response time Chapter Overview In Section Contents Page 7 1 Cycle Time 7 2 7 2 Response Time 7 6 7 3 Interrupt Response Time 7 9 Execution Times For the STEP 7 instructions that can be processed by the CPUs can be found in Appendix B For...

Page 100: ...le Time Factors Remarks Operating system execution time See Table 7 1 Process image transfer time PII and PIQ See Table 7 2 User program execution time Is calculated from the execution times of the individual instructions and a CPU specific factor see Table 7 3 S7 timers See Table 7 4 Loading through interrupts See Table 7 5 The following figure shows the components that make up the cycle time PII...

Page 101: ...s Load block delete block compress block Communication Table 7 1 Extending the Cycle by Nesting Interrupts Sequence IM 151 CPU Operating system processing time 540 s to 1040 s Process Image Transfer Time The table below contains the CPU times for process image updating process image transfer time The specified times are ideal values that get increased by interrupts that occur or by communication i...

Page 102: ...a the PROFIBUS DP between the DP master and DP slave input data output data 0 to 128 bytes The volume of data obtained through direct communication 0 to 256 bytes You can calculate the factor for your application approximately using the following rule of thumb for the IM 151 CPU 1 1 0 0055 x number of modules 0 0022 x number of bytes transfered PROFIBUS DP 0 0011 x number of bytes obtained direct ...

Page 103: ... analog output Extending the Cycle by Nesting Interrupts Table 7 5 shows typical extensions of the cycle time through nesting of an interrupt The program runtime at the interrupt level must be added to these If several interrupts are nested the corresponding times need to be added Table 7 5 Extending the Cycle by Nesting Interrupts Interrupts IM 151 CPU Process interrupt Approx 480 s Diagnostic in...

Page 104: ...rs The response time depends on the cycle time and the following factors Factors Remarks Delay of the inputs and outputs You can find the delay times in the technical specifications of the signal modules in the ET 200S Distributed I O Device manual Range of Fluctuation The actual response time lies between a shortest and a longest response time You must always reckon on the longest response time w...

Page 105: ...ge in the input signal is processed by the user program here The response of the user program to the input signal change is passed on to the outputs here Response Time Delay of the inputs Delay of the outputs Figure 7 2 Shortest Response Time Calculation The shortest response time consists of the following 1 process image transfer time for the inputs 1 operating system processing time 1 program sc...

Page 106: ...input signal is processed by the user program here The response of the user program to the input signal change is passed on to the outputs here Response Time Delay of the inputs Delay of the outputs Operating system User program PII PIQ Figure 7 3 Longest Response Time Calculation The longest response time consists of the following 2 process image transfer time for the inputs 2 process image trans...

Page 107: ...t Response Times Table 7 6 Interrupt Response Times of the IM 151 CPU Without Communication Interrupt Response Times Without Communication for Duration Process interrupt diagnostic interrupt Less than 20 ms Process Interrupt Handling Process interrupt handling begins when the process interrupt OB 40 is called Higher priority interrupts cause the process interrupt handling routine to be interrupted...

Page 108: ...Cycle and Response Times 7 10 ET 200S Interface Module IM 151 CPU A5E00058783 01 ...

Page 109: ...ules and regulations that vary depending on the application Please note the relevant safety and accident prevention regulations such as IEC 204 emergency stop systems Non compliance with these regulations can result in serious injury and damage to both machinery and equipment Chapter Overview In Section Contents Page 8 1 Step 1 Installing the ET 200S IM 151 CPU and S7 300 8 3 8 2 Step 2 Wiring the...

Page 110: ...00 0AA0 1 Digital input module DI e g 6ES7 131 4BD00 0AA0 1 Digital output module DO e g 6ES7 132 4BD00 0AA0 1 Terminal module TM for the PM e g 6ES7 193 4CC30 0AA0 2 Terminal modules TM for DI and DO e g 6ES7 193 4CB30 0AA0 1 Rail for ET 200S Various 1 Programming device PG with PROFIBUS DP interface installed STEP 7 software version 5 1 and PG cable up to 1 5 Mbps Various 1 PROFIBUS DP cable Var...

Page 111: ...51 CPU to the rail and tip it down until it snaps into position 4 Attach the TM for the PM to the rail on the right of the IM 151 CPU and tip it down until it snaps into position 5 Move the TM to the left until you can hear it engage with the IM 151 CPU 6 Repeat steps 3 and 4 with the two TMs for the electronic modules and then with the terminating module which doesn t snap onto the rail 7 Push th...

Page 112: ... terminal until it reaches the stop moving the screwdriver upwards slightly if necessary You can then insert a free cable end into the square hole below Remove the screwdriver and check that the cable is in position securely 5 Wire terminal 2 of the TM of the PM to L of the PS and terminal 3 of the TM of the PM to M of the PS Strip 11 mm from the cable ends and attach wire end ferrules 6 Wire term...

Page 113: ...Briefly press down the mode selector of the IM 151 CPU to MRES The STOP LED begins to flash rapidly and then comes on continuously This indicates that the memory reset has been completed The SF LEDs on the PM and IM 151 CPU go out 4 Operate the two switches connected to the DI When you operate the switch on terminals 1 and 3 the 1 LED lights up When you operate the switch on terminals 5 and 7 the ...

Page 114: ...is station ET 200S SIMATIC 300 1 is renamed ET 200S 5 Navigate in SIMATIC Manager to the ET 200S station Double click DUGZDUH in the right hand part of the window to open the hardware configuration editor 6 If a catalog is not displayed in the right hand part of the window activate the catalog by choosing the DWDORJ command from the 9LHZ menu Navigate to 7 6 in the catalog via 352 86 3 Insert the ...

Page 115: ...y dragging and dropping it onto slot 4 9 Do the same with the DI on slot 5 and the DO on slot 6 10 Double click 3 6ODYH line X2 in the lower left part of the window in the hardware configuration program Choose the 2SHUDWLQJ 0RGH tab in the dialog box that appears Select the 1R 3 check box on this tab Confirm with 2 11 Choose the 6DYH DQG RPSLOH command from the 6WDWLRQ menu The hardware configurat...

Page 116: ... current path The line is highlighted 5 Double click the button normally open contact on the toolbar and then click the button coil The icons are inserted into the rung current path 6 Click the red question mark of the normally open contact on the left in the rung current path The normally open contact is highlighted and a text box with a cursor appears at the point of the question mark 7 Enter an...

Page 117: ...oose the RZQORDG command to transfer the program and the hardware configuration to the CPU Click HV in all the dialog boxes that appear The program and configuration are downloaded from the programming device to the CPU 4 Switch the CPU mode selector to 581 3 The 6723 LED goes out The 581 LED starts flashing and then comes on continuously 5 Operate the two switches alternately The LEDs of the inpu...

Page 118: ...PU of the S7 300 using the PROFIBUS DP cable 1RWH At least one of the bus connectors has a piggy back connector Make sure that this connector is with the S7 300 CPU 5 Switch on the BUS terminating resistors on the connectors of the PROFIBUS DP cable 6 Connect the programming device to the MPI interface of the S7 300 CPU via the programming device cable 7 Secure all the connectors and close the fro...

Page 119: ...SHUDWLQJ 0RGH tab Select the 3 6ODYH option on this tab Confirm with 2 3 From the 6WDWLRQ menu choose the 6DYH DQG RPSLOH command Close the hardware editor The hardware configuration is compiled and saved and the editor is closed Configure the S7 300 CPU as shown below 6WDJH 3URFHGXUH 5HVXOW 1 In SIMATIC Manager select the HWWLQJ 6WDUWHG project in the left hand part of the window 2 Insert a new S...

Page 120: ...ame for the S7 300 CPU slot 2 the S7 300 DI slot 4 and the S7 300 DO slot 5 Note When you insert the S7 300 CPU a dialog box appears Select the PROFIBUS network from the window and set address 2 Confirm with 2 Configuration example might differ 7 Double click 38 3 line 2 in the lower left part of the hardware configuration program window In the dialog box that appears click the Properties button o...

Page 121: ...x that appears click the QWHUFRQQHFW button In the dialog box select the Configuration tab and fill it in as shown in the screen shot Confirm with 2 10 From the 6WDWLRQ menu choose the 6DYH DQG RPSLOH command Close the hardware editor The hardware configuration is compiled and saved and the editor is closed ...

Page 122: ...ger to the block container of the ET 200S Double click the 2 icon in the right hand part of the window The LAD FBD STL editor is opened to edit block OB1 2 Add to OB1 of the IM 151 CPU as shown below 3 Navigate in SIMATIC Manager to the block container of the S7 300 Double click the 2 icon in the right hand part of the window The LAD FBD STL editor is opened to edit block OB1 ...

Page 123: ...e PQB12 I O output byte You specified in the hardware configuration in step 8 Configuring the S7 300 stage 9 that the area from PQW12 to PQW44 in the S7 300 CPU is to be assigned to the area from PIW128 to PIW160 in the IM 151 CPU In the IM program PIB128 is transferred to the MB12 memory byte The memory marker M12 0 addresses output Q2 1 This results in the following communication paths 6 0 38 I1...

Page 124: ...ry reset for the S7 300 CPU as follows Turn the mode selector to the 05 6 position Keep the mode selector in this position until the 6723 LED lights up for the second time and stays on this takes 3 seconds Within the next 3 seconds you must turn the mode selector back to the 05 6 position The 6723 LED starts to flash rapidly and the CPU executes a memory reset When the 6723 LED comes on continuous...

Page 125: ...ainer of the ET 200S Select the block container in the left hand part of the window In SIMATIC Manager choose the RZQORDG command from the 3 menu to transfer the program and the hardware configuration to the IM 151 CPU Click HV in all the dialog boxes that appear The program and configuration are downloaded from the programming device to the CPU 9 Put the mode selector of the IM 151 CPU into the 5...

Page 126: ...y of the IM 151 CPU is deleted To download the program again you have the three following options 1 Download your program from the programming device to the IM 151 CPU 2 Store your program on the MMC in the IM 151 CPU STEP 7 3 menu RS 5 0 WR 520 menu command 3 Store your program on the MMC in the programming device STEP 7 3 menu 6DYH 3URMHFW RQ 3 0HPRU DUG menu command and insert the MMC in the IM...

Page 127: ...When you use an S7 master and configure and parameterize it with STEP 7 you are supported during input by STEP 7 and by the online help system You do not need the information in this appendix Configuration with Any Other Configuration Software If you enter the address areas of the intermediate memory of the CPU using a configuration and parameter assignment frame you will find the information you ...

Page 128: ...e IDs are constant Maximum area that can be displayed 0 64 bytes words of inputs 0 64 bytes words of outputs an asymmetrical configuration is possible The structure of the configuration frame in the special identifier format for the IM 151 CPU is as follows Table A 1 Structure of the Configuration Frame in the special identifier format SKF Config red Address Area Byte Configured Address Area n n 1...

Page 129: ...t Length 3 Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Input See Figure A 1 See Figure A 2 00H 83H 40H Output 00H 93H 40H Byte 0 7 0 Bit no 6 4 5 3 1 2 0011 Number of manufacturer specific data items bytes 2 3 and 4 in Table A 2 0 0 00 Spacesaver 01 1 byte length byte for input data follows 10 1 byte length byte for output data follows Figure A 1 Description of Byte 0 of the Address Area Identifiers Byte 1...

Page 130: ...f the intermediate memory of the CPU component The first three bytes of the configuration frame are always 0 This represents the 3 fixed 1 byte identifiers Maximum area that can be displayed 0 16 bytes words of inputs 0 16 bytes words of outputs an asymmetrical configuration is possible The structure of the configuration frame in the normal identifier format is as follows Table A 3 Structure of th...

Page 131: ...e configuration frame for the default setting 16 words of input data unit consistency i e word 16 words of output data unit consistency i e word Table A 4 Structure of the Configuration Frame with Default Setting for the Address Areas Normal Identifier Format in Accordance with AKF Configured Address Areas Byte 1 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 4 7 0 Bit no 6 4 5 3 1 2 Length o...

Page 132: ...e for the IM 151 CPU is 16 bytes Standard section bytes 0 to 6 Parameters of the IM 151 CPU bytes 7 to 15 Structure of the Standard Section The first 7 bytes of the parameter assignment frame are standardized to EN 50170 Volume 2 PROFIBUS and have the following contents Byte 3 Watchdog factor 1 Response delay TRDY Station status Watchdog factor 2 Manufacturer ID high byte Byte 0 Byte 1 Byte 2 Byte...

Page 133: ...e set by STEP 7 depends on the DP master Bit no 7 4 3 2 0 7 2 7 3 2 0 6 5 1 DPV1_Status_1 DPV1_Status_3 DPV1_Status_2 Bit no DataExchangeBroadcast 0 Check CFG mode STOP 1 Check CFG mode RUN resulting in PRM FAULT Update interrupt enable Status interrupt enable Manufacturer interrupt enable Diagnostic interrupt enable Process interrupt enable Module removal insertion interrupt enable Interrupt reso...

Page 134: ...Configuration Frame and Parameter Assignment Frame for the ET 200S A 8 ET 200S Interface Module IM 151 CPU A5E00058783 01 ...

Page 135: ...escriptions of all the instructions together with examples in the STEP 7 programming manuals Note In the case of indirect addressing for examples see Appendix B 4 you have to add the time for loading the address of the instruction to the execution times see Appendix B 5 Overview Appendix Contents Page B 1 Address Identifiers and Parameter Ranges B 2 B 2 Abbreviations B 3 B 3 Tab B 3 B 4 Addressing...

Page 136: ...n instance DB I 0 0 to 127 7 Input in PII IB 0 to 127 Input byte in PII IW 0 to 126 Input word in PII ID 0 to 124 Input double word in PII L 0 0 to 255 7 Local data LB 0 to 255 Local data byte LW 0 to 254 Local data word LD 0 to 252 Local data double word M 0 0 to 255 7 Memory markers MB 0 to 255 Memory byte MW 0 to 254 Memory word MD 0 to 252 Memory double word PQB 0 to 1535 Peripheral output byt...

Page 137: ...0 p Hexadecimal constant EA12 LABEL Symbolic jump address max 4 cha racters DEST B 3 Tab ACCU1 and ACCU2 32 Bits The accumulators are registers for processing bytes words or double words The address IDs are loaded into the accumulators where they are logically gated The result of the logic operation RLO is always in ACCU1 The accumulators are 32 bits long Accumulator designations ACCU Bit ACCU1 AC...

Page 138: ...bbbbbbb bbbbbxxx Area crossing address 10000yyy 00000bbb bbbbbbbb bbbbbxxx Legend b Byte address x Bit number y Area identifier see Appendix B 4 Status Word 16 Bits The status word bits are evaluated or set by the instructions The status word is 16 bits long Bit Assign ment Description 0 FC First check bit 1 RLO Result of previous logic operation 2 STA Status 3 OR Or 4 OS Stored overflow 5 OV Over...

Page 139: ...byte 1 into ACCU1 L IW 0 Load input word 0 into ACCU1 L ID 0 Load input double word 0 into ACCU1 Indirect Addressing of Timers Counters SP T LW 8 Start timer the timer number is in local data word 8 CU C LW 10 Start counter the counter number is in local data word 10 Area Internal Memory Indirect Addressing A I LD 12 Example L P 22 2 T LD 12 A I LD 12 AND operation The address of the input is in l...

Page 140: ...111 87Predecessor local data area access to local data of the calling block see page B 5 L B AR1 P 8 0 Load byte into ACCU1 The address is calculated from the pointer value in AR 1 P 8 0 A AR1 P 32 3 AND operation The address of the address ID is calculated from the pointer value in AR1 P 32 3 Addressing Via Parameters A Parameter Addressing via parameters Calculating Pointers Here are 2 examples ...

Page 141: ...g the address execution time of the instruction Total execution time of the instruction The execution times given in Appendix B 6 and the following chapters are the execution times for the second part of a statement i e for the actual execution of an instruction You then have to add the time required for loading the address of the instruction to this execution time Loading an Address The execution...

Page 142: ...on List B 8 ET 200S Interface Module IM 151 CPU A5E00058783 01 Address Is In Execution Time in s Parameter word for Timers Counters Block calls 2 1 Parameter double word for Bits bytes words and double words 4 3 ...

Page 143: ... Address Is In Execution Time in s Memory marker area M Word Double word 0 8 2 1 Data block DB DX Word Double word 3 0 4 1 Step 2 ANDing of the addressed input the execution time is in Appendix B 6 and the following chapters Typical Execution Time in s Direct Addressing Indirect Addressing 0 3 1 6 Time for A I Total Execution Time This results in a total execution time of 4 1 s 1 6 s 5 7 s ...

Page 144: ...1 and increment it by the offset 34 3 Address Is In Execution Time in s AR1 AR2 area internal 1 7 Step 2 ANDing of the addressed input the execution time is in Appendix B 6 and the following chapters Typical Execution Time in s Direct Addressing Indirect Addressing 0 3 1 6 Time for A I Total Execution Time This results in a total execution time of Total execution time 1 7 s 1 6 s 3 3 s ...

Page 145: ...ents of AR1 and increment it by the offset 23 1 Address Is In Execution Time in s AR1 AR2 area crossing 3 2 Step 2 ANDing of the addressed input the execution time is in Appendix B 6 and the following chapters Typical Execution Time in s Direct Addressing Indirect Addressing 0 3 1 6 Time for A I Total Execution Time This results in a total execution time of Total execution time 3 2 s 1 6 s 4 8 s ...

Page 146: ...g the I 0 5 addressed via the parameter Address Is In Execution Time in s Parameter double word 4 3 Step 2 ANDing of the addressed input the execution time is in Appendix B 6 and the following chapters Typical Execution Time in s Direct Addressing Indirect Addressing 0 3 1 6 Time for A I Total Execution Time This results in a total execution time of Total execution time 4 3 s 1 6 s 5 9 s ...

Page 147: ...5 0 8 1 0 3 1 1 9 2 1 2 2 2 8 AR1 m AR2 m Parameters I Q M L DBX DIX addressed area crossing via AR1 AR2 or via parameter 2 Status word for A AN BR A1 A0 OV OS OR STA RLO FC Instruction depends on Yes Yes Yes Instruction controls Yes Yes Yes 1 O I O M L DBX DIX OR Input output Memory markers Local data bit Data bit 1 2 1 2 2 2 0 3 0 7 0 9 2 9 1 6 1 7 1 8 2 5 AR1 m AR2 m Parameters I Q M L DBX DIX ...

Page 148: ... 2 9 1 6 1 7 1 9 2 5 AR1 m AR2 m Parameters I Q M L DBX DIX addressed area crossing via AR1 AR2 or via parameter 2 XN I O M L DBX DIX EXCLUSIVE OR NOT Input output Memory markers Local data bit Data bit 2 0 5 0 8 1 0 3 1 1 9 2 0 2 2 2 8 AR1 m AR2 m Parameters I Q M L DBX DIX addressed area crossing via AR1 AR2 or via parameter 2 Status word for X XN BR A1 A0 OV OS OR STA RLO FC Instruction depends...

Page 149: ...parenthesis 1 1 7 AN AND NOT left parenthesis 1 1 7 O OR left parenthesis 1 1 7 ON OR NOT left parenthesis 1 1 7 X EXCLUSIVE OR left parenthesis 1 1 7 XN EXCLUSIVE OR NOT left parenthesis 1 1 7 Status word for A AN O ON X XN BR A1 A0 OV OS OR STA RLO FC Instruction depends on Yes Yes Yes Yes Instruction controls 0 1 0 Right parenthesis removing an entry from the nesting stack gating the RLO with t...

Page 150: ...principle AND before OR In str c Address Description Length i Typical Execution Time in struc tion Address ID Description in Words Typical Execution Time in s O The ORing of AND functions is carried out according to the principle AND before OR 1 0 5 Status word for O BR A1 A0 OV OS OR STA RLO FC Instruction depends on Yes Yes Yes Instruction controls Yes 1 Yes ...

Page 151: ...ord for A AN BR A1 A0 OV OS OR STA RLO FC Instruction depends on Yes Yes Yes Instruction controls Yes Yes Yes 1 O T C OR timer OR counter 1 2 0 9 0 6 2 1 1 8 Timer para Counter p OR timer counter addressed via parameter 2 ON T C OR NOT timer OR NOT counter 1 2 1 1 0 9 2 3 2 1 Timer para Counter p OR NOT timer counter addressed via parameter 2 X T C EXCLUSIVE OR timer EXCLUSIVE OR counter 2 0 9 0 6...

Page 152: ... or ACCU1 L In struc tion Address ID Description Length in Words Typical Execution Time in s AW AND ACCU2 L 1 0 6 k16 AND 16 bit constant 2 0 9 OW OR ACCU2 L 1 0 6 k16 OR 16 bit constant 2 0 9 XOW EXCLUSIVE OR ACCU2 L 1 0 6 k16 EXCLUSIVE OR 16 bit con stant 2 0 9 AD AND ACCU2 1 2 0 k16 AND 16 bit constant 3 2 3 OD OR ACCU2 1 2 0 k16 OR 16 bit constant 3 2 3 XOD EXCLUSIVE OR ACCU2 1 2 0 k16 EXCLUSI...

Page 153: ... in s A 0 AND result 0 CC 1 0 and CC 0 0 1 0 6 0 AND result 0 CC 1 1 and CC 0 0 1 0 9 0 AND result 0 CC 1 0 and CC 0 1 1 0 9 0 AND result 0 CC 1 0 and CC 0 1 or CC 1 1 and CC 0 0 1 0 6 0 AND result 0 CC 1 0 and CC 0 1 or CC 1 0 and CC 0 0 1 0 6 0 AND result 0 CC 1 1 and CC 0 0 or CC 1 0 and CC 0 0 1 0 6 AO AND unordered CC 1 1 and CC 0 1 1 0 6 OS AND OS 1 1 0 3 BR AND BR 1 1 0 3 OV AND OV 1 1 0 3 ...

Page 154: ...0 and CC 0 1 1 0 9 0 AND NOT result 0 CC 1 0 and CC 0 1 or CC 1 1 and CC 0 0 1 0 9 0 AND NOT result 0 CC 1 0 and CC 0 1 or CC 1 0 and CC 0 0 1 0 3 0 AND NOT result 0 CC 1 1 and CC 0 0 or CC 1 0 and CC 0 0 1 0 3 AO AND NOT unordered CC 1 1 and CC 0 1 1 0 9 OS AND NOT OS 1 1 0 6 OV AND NOT OV 1 1 0 6 BR AND NOT BR 1 1 0 6 Status word for AN condition BR A1 A0 OV OS OR STA RLO FC Instruction depends ...

Page 155: ...esult 0 CC 1 0 and CC 0 1 1 0 9 0 OR result 0 CC 1 0 and CC 0 1 or CC 1 1 and CC 0 0 1 0 6 0 OR result 0 CC 1 0 and CC 0 1 or CC 1 0 and CC 0 0 1 0 6 0 OR result 0 CC 1 1 and CC 0 0 or CC 1 0 and CC 0 0 1 0 6 AO OR unordered CC 1 1 and CC 0 1 1 0 6 OS OR OS 1 1 0 3 OV OR OV 1 1 0 3 BR OR BR 1 1 0 3 Status word for O condition BR A1 A0 OV OS OR STA RLO FC Instruction depends on Yes Yes Yes Yes Yes ...

Page 156: ... 0 1 0 9 0 OR NOT result 0 CC 1 0 and CC 0 1 1 0 9 0 OR NOT result 0 CC 1 0 and CC 0 1 or CC 1 1 and CC 0 0 1 0 9 0 OR NOT result 0 CC 1 0 and CC 0 1 or CC 1 0 and CC 0 0 1 0 3 0 OR NOT result 0 CC 1 1 and CC 0 0 or CC 1 0 and CC 0 0 1 0 3 AO OR NOT unordered CC 1 1 and CC 0 1 1 0 9 OS OR NOT OS 1 1 0 6 OV OR NOT OV 1 1 0 6 BR OR NOT BR 1 1 0 6 Status word for ON condition BR A1 A0 OV OS OR STA RL...

Page 157: ...C 0 1 1 0 9 0 EXCLUSIVE OR result 0 CC 1 0 and CC 0 1 or CC 1 1 and CC 0 0 1 0 6 0 EXCLUSIVE OR result 0 CC 1 0 and CC 0 1 or CC 1 0 and CC 0 0 1 0 6 0 EXCLUSIVE OR result 0 CC 1 1 and CC 0 0 or CC 1 0 and CC 0 0 1 0 6 AO EXCLUSIVE OR unordered CC 1 1 and CC 0 1 1 0 6 OS EXCLUSIVE OR OS 1 1 0 3 OV EXCLUSIVE OR OV 1 1 0 3 BR EXCLUSIVE OR BR 1 1 0 3 Status word for X condition BR A1 A0 OV OS OR STA ...

Page 158: ...0 9 0 EXCLUSIVE OR NOT result 0 CC 1 0 and CC 0 1 or CC 1 1 and CC 0 0 1 0 9 0 EXCLUSIVE OR NOT result 0 CC 1 0 and CC 0 1 or CC 1 0 and CC 0 0 1 0 3 0 EXCLUSIVE OR NOT result 0 CC 1 1 and CC 0 0 or CC 1 0 and CC 0 0 1 0 3 AO EXCLUSIVE OR NOT unordered CC 1 1 and CC 0 1 1 0 9 OS EXCLUSIVE OR NOT OS 1 1 0 6 OV EXCLUSIVE OR NOT OV 1 1 0 6 BR EXCLUSIVE OR NOT BR 1 1 0 6 Status word for XN condition B...

Page 159: ...Words Direct Ad dressing Indirect Ad dressing FP I O M L DBX DIX Detection of the rising edge in the RLO The bit addressed in the instruction is the auxiliary edge memory marker 2 0 8 1 5 1 6 4 0 2 4 2 7 2 7 3 6 DBX DIX AR1 m AR2 m Parame ters 4 0 3 6 FN I O M L DBX DIX Detection of the falling edge in the RLO The bit addressed in the instruction is the auxiliary edge memory marker 2 1 0 1 6 1 7 4...

Page 160: ...parameter 2 R I O M L DBX DIX Reset input output to 0 MCR dependent Reset memory marker to 0 MCR dependent Reset local data bit to 0 MCR dependent Reset data bit to 0 MCR dependent 1 2 1 2 2 2 0 4 0 5 0 9 2 4 1 3 3 0 3 8 4 3 2 3 3 0 2 6 3 2 2 6 2 7 3 6 4 3 AR1 m AR2 m Parame ters Set I Q M L DBX DIX MCR dependent to 0 addressed area crossing via AR1 AR2 or via parameter 2 I O M L DBX DIX Assign RL...

Page 161: ...s word for CLR BR A1 A0 OV OS OR STA RLO FC Instruction depends on Instruction controls 0 0 0 0 SET Set RLO to 1 1 0 3 Status word for SET BR A1 A0 OV OS OR STA RLO FC Instruction depends on Instruction controls 0 1 1 0 NOT Negate RLO 1 0 3 Status word for NOT BR A1 A0 OV OS OR STA RLO FC Instruction depends on Yes Yes Instruction controls 1 Yes SAVE Save the RLO in the BR bit 1 0 3 Status word fo...

Page 162: ...r para change from 0 to 1 2 SD T Start timer as ON delay on edge change f 0 t 1 1 2 9 7 10 2 Timer para from 0 to 1 2 SS T Start timer as retentive ON delay on edge h f 0 t 1 1 2 9 7 10 2 Timer para change from 0 to 1 2 SF T Start timer as OFF delay on edge change f 1 t 0 1 2 10 0 10 5 Timer para from 1 to 0 2 FR T Enable timer for restarting on edge h f 0 t 1 t d 1 2 2 1 2 7 Timer para change fro...

Page 163: ... at edge h f 0 t 1 1 2 1 8 2 3 Counter p change from 0 to 1 2 CU C Increment counter by 1 on edge h f 0 t 1 1 2 2 8 3 4 Counter p change from 0 to 1 2 CD C Decrement counter by 1 on edge h f 0 t 1 1 2 3 0 3 5 Counter p change from 0 to 1 2 FR C Enable counter at edge change from 0 to 1 reset edge memory 1 2 2 2 2 7 Counter p from 0 to 1 reset edge memory marker for up and down counting of a counte...

Page 164: ...oad IB QB PIB MB LB DBB DIB into ACCU1 addressed via parameter 2 IW QW PIW Load Input word Output word Peripheral input byte 1 2 1 2 1 2 0 9 0 9 135 1 9 1 9 137 MW LW DBW Memory word Local data word Data word 1 2 2 2 1 1 1 3 3 3 2 1 2 3 3 2 DBW DIW Data word Instance data word in ACCU1 L 2 2 3 3 3 3 3 2 3 2 Parame ters Load IW QW PIW MW LW DBW DIW into ACCU1 addressed via parame ter 2 ID QD PID Lo...

Page 165: ...sed via parameter 2 2 n Load 16 bit binary constant in ACCU1 L 2 0 6 Load 32 bit binary constant in ACCU1 3 0 7 16 p Load 16 bit hexadecimal constant in ACCU1 L 2 0 6 Load 32 bit hexadecimal constant in ACCU1 3 0 7 xx Load 2 characters 2 0 7 xxxx Load 4 characters 3 0 88 D date Load IEC date binary coded decimal 2 0 8 S5T time value Load S5 time constant 16 bits 2 0 8 TOD time value Load 32 bit ti...

Page 166: ...rds Direct Ad dressing Indirect Ad dressing L T Load time value 1 2 1 7 2 1 Timer para Load time value addressed via parame ter 2 C Load count value 1 2 1 5 2 1 Counter p Load time value addressed via parame ter 2 LD T Load value of a timer binary coded deci mal 1 2 5 4 5 9 Timer para Load value of a timer binary coded deci mal addressed via the parameter 2 C Load count value binary coded decimal ...

Page 167: ...LL to Input byte MCR dependent Output byte MCR dependent Peripheral output byte MCR dependent 1 2 1 2 1 2 0 3 1 4 0 3 1 4 125 126 1 2 1 6 1 2 1 6 127 128 MB LB Memory byte MCR dependent Local data byte MCR dependent 1 2 2 2 0 4 1 5 0 6 1 8 1 3 1 7 1 5 2 0 DBB DIB MCR de endent Data byte MCR dependent Instance data byte MCR dependent 2 2 1 8 2 5 3 0 2 5 3 0 2 0 2 3 2 8 2 3 2 8 B AR1 µ B AR2 m Param...

Page 168: ...r contents of ACCU1 L to IW QW PQW MW LW DBW DIW addressed via AR1 AR2 area crossing or via parame ter 2 ID QD PQD Transfer contents of ACCU1 to Input double word MCR dependent Output double word MCR dependent Peripheral output double word MCR dependent 1 2 1 2 2 0 8 1 8 0 8 1 8 150 151 1 7 2 1 1 7 2 1 152 153 MD LD Memory double word MCR dependent Local data double word MCR dependent 1 2 2 1 3 2 ...

Page 169: ... as pointer Local data double word Memory double word into AR1 1 1 2 2 3 2 2 0 3 0 3 3 8 3 8 0 5 1 5 1 4 LAR2 DBD DID m LD MD Load contents from ACCU1 Data double word Instance data double word 32 bit constant as pointer Local data double word Memory double word into AR2 1 2 2 3 2 2 0 3 3 8 3 8 0 5 1 5 1 4 TAR1 AR2 DBD DID LD MD Transfer contents of AR1 to ACCU1 Address register 2 Data double word...

Page 170: ...word 1 4 Status word for T STW BR A1 A0 OV OS OR STA RLO FC Instruction depends on Instruction controls Yes Yes Yes Yes Yes 0 0 Yes 0 Structure of the Status Word B 22 Load Instructions for DB Numbers and DB Length Load the number length of a data block into ACCU1 The contents of ACCU1 are saved to ACCU2 first The indicators are not affected In struc tion Address ID Description Length in Words Typ...

Page 171: ...in Words Typical Execution Time in s I Add 2 integers 16 bits ACCU1 L ACCU1 L ACCU2 L 1 1 5 I Subtract 2 integers 16 bits ACCU1 L ACCU2 L ACCU1 L 1 1 6 I Multiply 2 integers 16 bits ACCU1 L ACCU2 L ACCU1 L 1 2 4 I Divide 2 integers 16 bits ACCU1 L ACCU2 L ACCU1 L The remainder of the division is in ACCU1 H 1 3 4 Status word for I I I I BR A1 A0 OV OS OR STA RLO FC Instruction depends on Instructio...

Page 172: ...me in s D Add 2 integers 32 bits ACCU1 ACCU2 ACCU1 1 2 0 D Subtract 2 integers 32 bits ACCU1 ACCU2 ACCU1 1 2 7 D Multiply 2 integers 32 bits ACCU1 ACCU2 ACCU1 1 9 9 D Divide 2 integers 32 bits ACCU1 ACCU2 ACCU1 1 10 8 MOD Divide 2 integers 32 bits and load the re mainder of the division in ACCU1 ACCU1 Remainder from ACCU2 ACCU1 1 11 3 Status word for D D D D MOD BR A1 A0 OV OS OR STA RLO FC Instru...

Page 173: ...CU2 ACCU1 1 35 R Divide 2 real numbers 32 bits ACCU1 ACCU2 ACCU1 1 40 Status word for R R R R BR A1 A0 OV OS OR STA RLO FC Instruction depends on Instruction controls Yes Yes Yes Yes NEGR Negate real number in ACCU1 1 0 3 ABS Make absolute value of the real number in ACCU1 1 0 3 Status word for NEGR ABS BR A1 A0 OV OS OR STA RLO FC Instruction depends on Instruction controls B 26 Addition of Const...

Page 174: ...to AR1 1 0 3 AR1 m Add pointer constant to AR1 2 0 3 AR2 Add contents of ACCU1 L to AR2 1 0 3 AR2 m Add pointer constant to AR2 2 0 3 B 28 Comparison Instructions with Integers 16 Bits Comparison of the integers 16 bits in ACCU1 L and ACCU2 L RLO 1 if the condition is satisfied In struc tion Address ID Description Length in Words Typical Execution Time in s I ACCU2 L ACCU1 L 1 1 4 I ACCU2 L ACCU1 ...

Page 175: ...and ACCU2 RLO 1 if the condition is satisfied In struc tion Address ID Description Length in Words Typical Execution Time in s D ACCU2 ACCU1 1 2 0 D ACCU2 ACCU1 1 2 0 D ACCU2 ACCU1 1 2 0 D ACCU2 ACCU1 1 2 0 D ACCU2 ACCU1 1 2 0 D ACCU2 ACCU1 1 2 0 Status word for D D D D D D BR A1 A0 OV OS OR STA RLO FC Instruction depends on Instruction controls Yes Yes 0 0 Yes Yes 1 ...

Page 176: ...satisfied The execution time of the instruction depends on the value to be compared In struc tion Address ID Description Length in Words Typical Execution Time in s R ACCU2 ACCU1 1 45 R ACCU2 ACCU1 1 45 R ACCU2 ACCU1 1 45 R ACCU2 ACCU1 1 45 R ACCU2 ACCU1 1 45 R ACCU2 ACCU1 1 45 Status word for R R R R R R BR A1 A0 OV OS OR STA RLO FC Instruction depends on Instruction controls Yes Yes Yes Yes 0 Ye...

Page 177: ... Length in Words Typical Execution Time in s SLW Shift the contents of ACCU1 L to the left 1 2 0 SLW 0 to 15 0 7 SLD Shift the contents of ACCU1 to the left 1 3 1 SLD 0 to 32 3 1 SRW Shift the contents of ACCU1 L to the right 1 2 0 SRW 0 to 15 0 7 SRD Shift the contents of ACCU1 to the right 1 3 1 SRD 0 to 32 3 1 SSI Shift the contents of ACCU1 L with sign to th i ht 1 1 8 SSI 0 to 15 the right 0 ...

Page 178: ...D Rotate the contents of ACCU1 to the left 1 3 3 RLD 0 to 32 3 4 RRD Rotate the contents of ACCU1 to the right 1 3 5 RRD 0 to 32 3 5 Status word for RLD RRD BR A1 A0 OV OS OR STA RLO FC Instruction depends on Instruction controls Yes Yes Yes RLDA Rotate the contents of ACCU1 one bit posi tion to the left through condition code bit CC 1 1 9 RRDA Rotate the contents of ACCU1 one bit posi tion to the...

Page 179: ... the contents of ACCU1 and ACCU2 1 0 8 PUSH The contents of ACCU1 are transferred to ACCU2 1 0 3 POP The contents of ACCU2 are transferred to ACCU1 1 0 3 INC 0 to 255 Increment ACCU1 LL 1 0 3 DEC 0 to 255 Decrement ACCU1 LL 1 0 3 B 34 Program Display and Null Operation Instructions Status Word The status word is not affected In struc tion Ad dress ID Description Length in Words Typical Execution T...

Page 180: ...ger 32 bits Int To Doubleint 1 0 1 Status word for BTI BTD DTR ITD BR A1 A0 OV OS OR STA RLO FC Instruction depends on Instruction controls ITB Convert contents of ACCU1 from integer 16 bits to BCD Int To BCD 1 5 1 DTB Convert contents of ACCU1 from double integer 32 bits to BCD Doubleint To BCD 1 11 8 Status word for ITB DTB BR A1 A0 OV OS OR STA RLO FC Instruction depends on Instruction controls...

Page 181: ...lement of ACCU1 L 1 0 3 INVD Create ones complement of ACCU1 1 0 3 Status word for INVI INVD BR A1 A0 OV OS OR STA RLO FC Instruction depends on Instruction controls NEGI Create twos complement of ACCU1 L 16 bit integer 1 1 5 NEGD Create twos complement of ACCU1 32 bit integer 1 2 0 Status word for NEGI NEGD NEGR BR A1 A0 OV OS OR STA RLO FC Instruction depends on Instruction controls Yes Yes Yes ...

Page 182: ...ithout para meters 1 2 5 3 6 1 Status word for CALL UC BR A1 A0 OV OS OR STA RLO FC Instruction depends on Instruction controls 0 0 1 0 CC FC Conditional call of blocks without parame ters 1 2 5 3 6 1 Status word for CC BR A1 A0 OV OS OR STA RLO FC Instruction depends on Yes Instruction controls 0 0 1 0 OPN DB Open a data block 2 1 5 2 6 DB para Open a data block addressed via parame ter 2 DI Open...

Page 183: ...truction depends on Instruction controls 0 0 1 0 BEC End block conditionally if RLO 1 3 2 Status word for BEC BR A1 A0 OV OS OR STA RLO FC Instruction depends on Yes Instruction controls Yes 0 1 1 0 B 39 Exchanging Data Blocks Exchange of the two current data blocks The current data block becomes the current instance data block and vice versa The indicators are not affected In struc tion Address I...

Page 184: ...s JU LABEL Jump unconditionally 1 2 1 8 Status word for JU BR A1 A0 OV OS OR STA RLO FC Instruction depends on Instruction controls JC LABEL Jump if RLO 1 1 2 1 5 JCN LABEL Jump if RLO 0 2 1 6 Status word for JC JCN BR A1 A0 OV OS OR STA RLO FC Instruction depends on Yes Instruction controls 0 1 1 0 JCB LABEL Jump if RLO 1 Save the RLO in the BR bit 2 1 8 JNB LABEL Jump if RLO 0 Save the RLO in th...

Page 185: ...f result 0 CC 1 0 and CC 0 1 1 2 1 8 JN LABEL Jump if result 0 CC 1 1 and CC 0 0 or CC 1 0 and CC 0 1 1 2 1 8 JMZ LABEL Jump if result 0 CC 1 0 and CC 0 1 or CC 1 0 and CC 0 0 2 1 5 JPZ LABEL Jump if result 0 CC 1 1 and CC 0 0 or CC 1 0 and CC 0 0 2 1 6 Status word for JUO JZ JP JM JN JMZ JPZ BR A1 A0 OV OS OR STA RLO FC Instruction depends on Yes Yes Instruction controls JL LABEL Jump distributor...

Page 186: ...ruc tion Address ID Description Length in Words Typical Execution Time in s MCR Open a MCR zone Save the RLO to the MCR stack 1 1 7 Status word for MCR BR A1 A0 OV OS OR STA RLO FC Instruction depends on Yes Instruction controls 0 1 0 MCR Close an MCR zone Remove an entry from the MCR stack 1 1 6 Status word for MCR BR A1 A0 OV OS OR STA RLO FC Instruction depends on Instruction controls 0 1 0 MCR...

Page 187: ...2 3 CTRL_RTM Starts stops the operating hours counter 57 4 READ_RTM Reads the operating hours counter 86 5 GADR_LGC Reads the free address of the channel x of the signal module on module slot y 148 6 RD_SINFO Read the start information of the current OB 116 3 per byte 7 DP_PRAL Triggers a process interrupt from the user program of the CPU as DP slave through to DP master 228 14 DPRD_DAT Reads cons...

Page 188: ...dling of new interrupts 702 41 DIS_AIRT Delays the handling of interrupts 48 42 EN_AIRT Enables the handling of interrupts 76 43 RE_TRIGR Re triggers cycle time monitoring 95 44 REPL_VAL Copies a replacement value into accumulator 1 of the level causing the error 51 46 STP Forces the CPU into STOP mode No value 47 WAIT Implements waiting times 861 49 LGC_GADR Converts a free address to the slot an...

Page 189: ...ith an accuracy of 10 ms 50 81 UBLKMOV Copies the variable without interruption 140 C 2 System Function Blocks SFBs SFB No Name Description Execution Time in s IEC Counters 0 CTU Counts up The counter is incremented by 1 for each rising edge 70 1 CTD Counts down The counter is decremented by 1 for each rising edge 69 2 CTUD Counts up and count down 85 IEC Timers 3 TP Generates a pulse of duration ...

Page 190: ...Execution Times of the SFCs and SFBs C 4 ET 200S Interface Module IM 151 CPU A5E00058783 01 ...

Page 191: ...7 300 SIMATIC family We will also show you how to rewrite programs you have written for the S7 300 CPUs for the IM 151 CPU Chapter Overview In Section Contents Page D 1 Differences to Selected S7 300 CPUs D 2 D 2 Porting the User Program D 3 More Information You can find further information on how to create and structure programs in the STEP 7 manuals and online help system D ...

Page 192: ...of 10 99 12 4 as of 10 99 12 5 Setting the PROFIBUS address Hardware configuration Hardware configuration Hardware configuration must match address setter Transmission rate to programming device and operator panel 187 5 kbps MPI 187 5 kbps MPI 12 Mbps DP 12 Mbps DP Interface Active Active Passive Communication Programming device operator panel Global data communication S7 basic communication S7 co...

Page 193: ...to an intelligent slave depend on how the address assignment of inputs and outputs is stored in the FBs in the source program The inputs and outputs can be used in the FCs in the source program in different ways Addresses can be packed in the current ET 200S which is not possible in the IM 151 CPU See the description of IM 151 CPU addressing in Section 2 1 Porting with Unpacked Addresses If you us...

Page 194: ...2 I1 3 O1 0 O1 1 DI_1_module DI_2_module Figure D 2 Example FB with Packed Addresses Rewiring The following blocks and address IDs can be reassigned Inputs outputs Memory markers timers counters Functions function blocks Proceed as follows to rewire the signals 1 In SIMATIC Manager select the Blocks folder which contains the blocks with the packed addresses that you want to port to the IM 151 CPU ...

Page 195: ...nals If you assign symbols to the inputs and outputs using the symbol table in STEP 7 you must change the symbol table to adjust the subprogram for use in the IM 151 CPU See also the STEP 7 online help system Porting FBs with I Os in an I O Word If you map the addresses of the inputs and outputs via an I O word to a function block you have programmed porting is considerably more involved It is pos...

Page 196: ...Migration of the IM 151 CPU D 6 ET 200S Interface Module IM 151 CPU A5E00058783 01 ...

Page 197: ... system is a programmable logic controller consisting of at least one CPU various input and output modules and operator interfaces Backup Memory The backup memory is for memory areas of the CPU without a backup battery A configurable number of timers counters memory markers and data bytes retentive timers counters memories and data bytes is backed up Bus A common transmission path connecting all n...

Page 198: ...ent times Counter Counters are part of the system memory of the CPU The content of the counter cells can by modified by STEP 7 instructions e g count up down CPU Central processing unit of the S7 programmable controller with a control unit and arithmetic logic unit memory operating system and interface for a programming device Cycle Time The cycle time is the time taken by the CPU to scan the user...

Page 199: ...stic interrupt block OB 82 In SIMATIC S5 The diagnostic interrupt appears in the station diagnosis Using cyclical querying of the diagnostic bits in the station diagnosis you can detect errors such as a wire break Diagnostics Diagnostics is the detection localization classification display and further evaluation of errors faults and messages Diagnostics includes monitoring functions that run autom...

Page 200: ...olume 2 PROFIBUS is referred to as a DP master DP Slave A slave on the PROFIBUS bus system with the PROFIBUS DP protocol that complies with EN 50170 Volume 2 PROFIBUS standard is referred to as a DP slave DP Standard The DP standard is the bus protocol of the ET 200 distributed I O system based on EN 50170 Volume 2 PROFIBUS Error Display The error display is one of the possible responses of the op...

Page 201: ... of DP masters are the IM 308 C master interface module and the CPU 315 2 DP DP slaves can be the distributed I O devices ET 200S ET 200B ET 200C ET 200M ET 200X ET 200U ET 200L or DP slaves from Siemens or other vendors FC Function Force During commissioning for example the Force function allows certain outputs to be set to ON for any length of time even if the logic operations of the user progra...

Page 202: ...lasses that control the processing of the user program These runtime levels include interrupts e g diagnostic interrupts When an interrupt is triggered the operating system automatically calls an assigned organization block in which the user can program the desired response for example in an FB Interrupt Diagnostic Diagnostic Interrupt Interrupt Process Process Interrupt Load Memory The load memor...

Page 203: ...er of code blocks called at the same time Node A device that can send receive or amplify data via the bus such as a DP master DP slave RS 485 repeater or active star coupler OB Organization Block OB Priority The operating system of the CPU distinguishes between various priority classes such as cyclic program scanning and process interrupt driven program scanning Each priority class is assigned org...

Page 204: ...odule is delivered with a suitable default setting which can be changed by configuring the parameters in STEP 7 PG Programming Device PLC Programmable Controller Priority Class The operating system of an S7 CPU provides up to 26 priority classes or runtime levels to which various organization blocks are assigned The priority classes determine which OBs interrupt other OBs If a priority class inclu...

Page 205: ...ers whose function is saved as a program in the control unit The configuration and wiring of the unit are therefore independent of the function of the control system The programmable logic controller has the structure of a computer it consists of the CPU central processing unit with memory input and output modules and an internal bus system The I Os and the programming language are designed for th...

Page 206: ...ss image is updated for example SFC System Function Slave A slave can only exchange data with a master when requested by it to do so By slaves we mean for example all DP slaves such as ET 200S ET 200B ET 200X ET 200M etc Stand Alone Operation The device is operated on a stand alone basis without data exchange to a superordinate master and without direct communication with other DP slaves All the m...

Page 207: ...main unchanged After each new SYNC control command the DP slave sets the outputs that it has saved as output data The outputs are not cyclically updated again until the DP master sends the UNSYNC control command System Diagnostics System diagnostics is the term used to describe the detection evaluation and indication of errors which occur within the programmable controller Examples of such errors ...

Page 208: ...he ET 200S transmission rates of 9 6 kbps to 12 Mbps are possible User Memory The user memory contains the code and data blocks of the user program The user memory can be integrated in the CPU IM 151 CPU or can be provided on plug in memory cards or memory modules The user program is always executed in the working memory of the CPU however User Program The SIMATIC system distinguishes between the ...

Page 209: ...etting 2 10 for user data transfer 2 7 of the expansion modules 2 3 Address assignment for analog and digital modules 2 3 Address identifiers B 2 Address registers B 4 Addresses base address 2 5 for diagnostics 2 7 for user data transfer 2 7 Addressing 2 1 address allocation 2 5 indirect B 7 interface in STEP 7 2 9 rules 2 9 slot oriented 2 2 user defined 2 5 Addressing examples STEP 7 instruction...

Page 210: ...nt Glossary 2 Data block Glossary 2 Data consistency 2 7 2 8 Data exchange direct 3 10 Data interchange sample program 2 10 Data transfer principle behind 2 1 with the DP master 2 6 DBs 5 13 DDB device database file 5 2 DEC B 45 Default addressing 2 2 Default setting A 5 for the address area 2 10 Delay of the inputs outputs 7 5 Device database file Glossary 2 Diagnosis module 4 20 station 4 14 4 2...

Page 211: ...circuit diagram 6 4 terminal assignment 6 3 IM 151 CPU interface module 6 4 basic circuit diagram 6 4 technical specifications 6 5 INC B 45 Inputs delay time 7 5 Installation 8 1 8 4 Integrated clock 5 12 Intelligent DP slave 4 2 Glossary 6 Intermediate memory accessing in the user program 2 8 in the IM 151 CPU 2 6 Internode communication see direct communication 3 10 Interrupt 4 14 Glossary 6 pro...

Page 212: ...e address 5 17 MRES mode selector 5 4 N NEGD B 47 NEGI B 47 Nesting depth Glossary 7 Network structure 3 1 Network components 3 7 Node Glossary 7 NOP B 45 NOT B 27 O O B 13 B 16 B 21 O B 15 OB Glossary 8 start event Glossary 10 OB 1 5 14 OB 100 5 14 OB 122 4 12 5 15 OB 40 4 14 5 14 OB 82 4 8 4 12 5 14 OB 86 4 8 4 12 5 15 OB priority Glossary 7 OB10 5 14 OB121 5 15 OB20 5 14 OB35 5 14 OB80 5 15 OB8...

Page 213: ...vice connecting cable 3 7 Programming device functions 3 9 Programming software 1 4 Publisher Glossary 9 PUSH B 45 R R B 26 B 28 B 29 Response time 7 6 diagnostic interrupt 7 9 longest 7 8 process interrupt 7 9 shortest 7 7 Restart Glossary 10 OB 100 5 14 Retentivity 5 16 Rewiring D 4 RLD B 44 RLDA B 44 RND B 46 RND B 46 RND B 46 RRD B 44 RRDA B 44 Rules for addressing 2 9 RUN LED 5 5 mode 5 5 RUN...

Page 214: ... B 34 B 36 TAK B 45 TAR1 B 35 TAR2 B 35 Technical specifications general 6 2 of the IM 151 CPU 6 2 PROFIBUS DP 5 2 Test functions 3 9 Test run 8 1 8 2 8 10 8 17 Time of day interrupts 5 16 Timers timer cells Glossary 12 Token Glossary 12 Transfer instruction 2 8 Transmission rate Glossary 12 Troubleshooting 4 1 TRUNC B 46 U UC B 48 Updating of the S7 timers 7 4 Upgrading 8 1 8 11 User data transfe...

Page 215: ...Republic of Germany From Your Name Your Title Company Name Street City Zip Code Country Phone Please check any industry that applies to you Automotive Chemical Electrical Machinery Food Instrument and Control Nonelectrical Machinery Petrochemical Pharmaceutical Plastic Pulp and Paper Textiles Transportation Other ...

Page 216: ...available opportunity to fill out this que stionnaire and return it to Siemens Please give each of the following questions your own personal mark within the range from 1 very good to 5 poor 1 Do the contents meet your requirements 2 Is the information you need easy to find 3 Is the text easy to understand 4 Does the level of technical detail meet your requirements 5 Please rate the quality of the ...

Page 217: ...Republic of Germany From Your Name Your Title Company Name Street City Zip Code Country Phone Please check any industry that applies to you Automotive Chemical Electrical Machinery Food Instrument and Control Nonelectrical Machinery Petrochemical Pharmaceutical Plastic Pulp and Paper Textiles Transportation Other ...

Page 218: ...available opportunity to fill out this que stionnaire and return it to Siemens Please give each of the following questions your own personal mark within the range from 1 very good to 5 poor 1 Do the contents meet your requirements 2 Is the information you need easy to find 3 Is the text easy to understand 4 Does the level of technical detail meet your requirements 5 Please rate the quality of the ...

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