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Siemens CPU 412, Instruction Manual

The Siemens CPU 412 is an advanced industrial control unit designed for precision automation. To ensure optimal performance, it is crucial to have the Instruction Manual at hand. You can conveniently download the free manual from our website, manualshive.com, to fully utilize the capabilities of this exceptional product.

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S7-400 Instruction List

CPU 412, 414, 416, 417

This Instruction List has the order number:

6ES7498-8AA04-8BN0

Edition 04/2004

A5E00267845-01

Summary of Contents for CPU 412

Page 1: ...S7 400 Instruction List CPU 412 414 416 417 This Instruction List has the order number 6ES7498 8AA04 8BN0 Edition 04 2004 A5E00267845 01 ...

Page 2: ... of Liability Copyright Siemens AG 2004 All rights reserved The reproduction transmission or use of this document or its contents is not permitted without express written authority Offenders will be liable for damages All rights including rights created by patent grant or registration of a utility model or design are reserved Siemens AG Bereich Automation and Drives Geschaeftsgebiet Industrial Aut...

Page 3: ... Ranges 9 Abbreviations and Mnemonics 10 Abbreviations and Mnemonics continued 11 Registers 12 Examples of Addressing 15 Examples of Addressing continued 17 Examples of how to calculate the pointer 18 Execution Times with Indirect Addressing1 19 Examples of Calculations 21 List of Instructions 24 Bit Logic Instructions 25 Bit Logic Instructions with Parenthetical Expressions 28 Bit Logic Instructi...

Page 4: ... Triggered Instructions 38 Setting Resetting Bit Addresses 39 Instructions Directly Affecting the RLO 41 Timer Instructions 42 Counter Instructions 45 Load Instructions 47 Load Instructions for Timers and Counters 53 Transfer Instructions 54 Load and Transfer Instructions for Address Registers 57 Load and Transfer Instructions for the Status Word 59 Load Instructions for DB Number and DB Length 60...

Page 5: ...nstructions 16 Bit Integers 72 Comparison Instructions 32 Bit Integers 73 Comparison Instructions 32 Bit Real Numbers 74 Shift Instructions 75 Rotate Instructions 77 Accumulator Transfer Instructions Incrementing and Decrementing 79 Accumulator Transfer Instructions Incrementing and Decrementing continued 80 Program Display and Null Operation Instructions 81 Data Type Conversion Instructions 82 Fo...

Page 6: ...and Instance Data Block 90 Jump Instructions 91 Instructions for the Master Control Relay MCR 97 Oganization Blocks OB 99 Function Blocks FB 104 Functions FC and Data Blocks 105 System Functions 106 System Function Blocks 139 Sublist of the System Status List SSL 148 Alphabetical Index of Instructions 154 ...

Page 7: ...B0 CPU 412 CPU 412 2 6ES7412 2XG04 0AB0 CPU 412 CPU 414 2 6ES7414 2XG04 0AB0 CPU 414 3 6ES7414 3XJ04 0AB0 CPU 414 CPU 414 4H 6ES7414 4HJ04 0AB0 CPU 414 CPU 416 2 6ES7416 2XK04 0AB0 CPU 416F 2 6ES7416 2FK04 0AB0 CPU 416 CPU 416 3 6ES7416 3XL04 0AB0 CPU 416 CPU 417 4 6ES7417 4XL04 0AB0 CPU 417 CPU 417 4 H 6ES7417 4HL04 0AB0 CPU 417 except in the tables where a detailled differentiation is necessary ...

Page 8: ...ock DB 1 to 511 1 to 4095 1 to 4095 1 to 8191 Data block DBB 0 to 65533 0 to 65533 0 to 65533 0 to 65533 Data byte in DB DBW 0 to 65532 0 to 65532 0 to 65532 0 to 65532 Data word in DB DBD 0 to 65530 0 to 65530 0 to 65530 0 to 65530 Data double word in DB DIX 0 0 to 65533 7 0 0 to 65533 7 0 0 to 65533 7 0 0 to 65533 7 Data bit in instance DB DI 1 to 511 1 to 4095 1 to 4095 1 to 8191 Instance data ...

Page 9: ...252 0 to 508 0 to 1020 Input double word in PII L 0 0 to 4095 7 0 0 to 8191 7 0 0 to 16383 7 0 0 to 32767 7 Local data LB 0 to 4095 0 to 8191 0 to 16383 0 to 32767 Local data byte LW 0 to 4094 0 to 8190 0 to 16382 0 to 32766 Local data word LD 0 to 4092 0 to 8188 0 to 16380 0 to 32764 Local data double word M 0 0 to 4095 7 0 0 to 8191 7 0 0 to 16383 7 0 0 to 16383 7 Bit memory MB 0 to 4095 0 to 81...

Page 10: ...0 0 to 16382 0 to 16382 Peripheral output word direct I O access PQD 0 to 4092 0 to 8188 0 to 16380 0 to 16380 Peripheral output double word direct I O access PIB 0 to 4095 0 to 8191 0 to 16383 0 to 16383 Peripheral input byte direct I O access PIW 0 to 4094 0 to 8190 0 to 16382 0 to 16382 Peripheral input word direct I O access PID 0 to 4092 0 to 8188 0 to 16380 0 to 16380 Peripheral output doubl...

Page 11: ...3 b4 Constant 2 or 4 bytes D Date IEC date constant L Integer 32 bit integer constant P Bit pointer Pointer constant S5T Time value S7 time constant 1 T TIme value Time constant TOD Time value IEC time constant C Count value Counter constant BCD code 2 n Binary constant W 16 DW 16 Hexadecimal constant 1 For loading of S7 timers ...

Page 12: ... 8 bit constant 0 to 255 32 k16 16 bit constant 256 to 32 767 28 131 k32 32 bit constant 32 768 to 999 999 999 127 624 i8 8 bit integer 128 to 127 113 i16 16 bit integer 32768 to 32767 6523 i32 32 bit integer 2 147 483 648 to 2 147 483 647 2 222 222 m Pointer constant P 240 3 n Binary constant 1001 1100 p Hexadecimal constant EA12 Label Symbolic jump address max 4 characters DESTINATION a Byte add...

Page 13: ...continued Abbrev Description Example b Bit address c Address area I Q M L DBX DIX d Address in MD DBD DID or LD e Number in MW DBW DIW or LW f Timer counter No g Address area IB QB PIB PQB MB LB DBB DIB h Address area IW QW PIW PQW MW LW DBW DIW i Address area ID QD PID PQD MD LD DBD DID q Block No ...

Page 14: ...re loaded into the accumulators where they are logically gated The result of the logic operation RLO is in ACCU1 and can be transferred from there to a memory cell The accumulators are 32 bits long Accumulator designations ACCU Bits ACCUx x 1 to 4 Bit 0 to 31 ACCUx L Bit 0 to 15 ACCUx H Bit 16 to 31 ACCUx LL Bit 0 to 7 ACCUx LH Bit 8 to 15 ACCUx HL Bit 16 to 23 ACCUx HH Bit 24 to 31 ...

Page 15: ...inters for instructions using indirect addressing The address registers are 32 bits long The area internal and or area crossing pointers have the following syntax Area internal pointer 00000000 00000bbb bbbbbbbb bbbbbxxx Area crossing pointer yyyyyyyy 00000bbb bbbbbbbb bbbbbxxx Legend b Byte address x Bit number y Area identifier see Examples of Addressing ...

Page 16: ...luated or set by the instructions The status word is 16 bits long Bit Assignment Description 0 FC First check bit 1 RLO Result of logic operation 2 STA Status 3 OR Or AND before OR 4 OS Stored overflow 5 OV Overflow 6 CC 0 Condition code 0 7 CC 1 Condition code 1 8 BR Binary result 9 to 15 Unassigned ...

Page 17: ... Load binary constant into ACCU1 L DW 16 A0F0BCFD Load hexadecimal constant into ACCU1 L ENDE Load ASCII character into ACCU1 L T 500 ms Load time value into ACCU1 L C 100 Load count value into ACCU1 L B 100 12 Load 2 byte constant L B 100 12 50 8 Load 4 byte constant L P 10 0 Load area internal pointer into ACCU1 L P E20 6 Load area crossing pointer into ACCU1 L 2 5 Load real number into ACCU1 L ...

Page 18: ...l data word 8 CU C LW 10 Count upwards the counter number is in local data word 10 Area Internal Memory Indirect Addressing A I LD 12 Example L P 22 2 T LD 12 A I LD 12 AND operation The address of the input is in local data double word 12 as pointer A I DBD 1 AND operation The address of the input is in data double word 1 of the open DB as pointer A I DID 12 AND operation The address of the outpu...

Page 19: ... contain an area identifier The address is in the address register The area identifiers are as follows Area Coding Area identifier binary hex P 1000 0000 80 I O area I 1000 0001 81 Input area Q 1000 0010 82 Output area M 1000 0011 83 Bit memory area DB 1000 0100 84 Data area DI 1000 0101 85 Instance data area L 1000 0110 86 Local data area VL 1000 0111 87 Predecessor local data area access to loca...

Page 20: ...o calculate the pointer Example for sum of bit addresses x7 LAR1 P 8 2 A I AR1 P 10 2 Result Input 18 4 is addressed by adding the byte and bit addresses Example for sum of bit addressesu7 L P 10 5 LAR1 A I AR1 P 10 7 Result Input 21 4 is addressed by adding the byte and bit addresses with carry over ...

Page 21: ...on time of an instruction from these two parts Calculating the Execution Time The total execution time is calculated as follows Time required for loading the address execution time of the instruction Total execution time of the instruction The execution times listed in the chapter entitled List of Instructions apply to the execution times of the second part of an instruction i e for the actual exe...

Page 22: ... 0 18 0 18 0 12 0 12 0 12 0 12 Local data area L Word Double word 0 2 0 2 0 12 0 12 0 08 0 08 0 06 0 06 AR1 AR2 area internal 0 0 0 0 0 0 0 0 AR1 AR2 area crossing 0 0 0 0 0 0 0 0 Parameter word for S Timers S Counters S Block calls 0 4 0 4 0 4 0 24 0 24 0 24 0 16 0 16 0 16 0 15 0 15 0 15 Parameter double word for Bits bytes words and double words 0 4 0 24 0 16 0 15 Address registers AR1 AR2 do no...

Page 23: ... 12 with CPU 414 Step 1 Load the contents of DBD 12 time required is listed in the table on page 20 Address is in Execution Time in s Bit memory area M Word Double word 0 2 0 3 Data block DB DX Word Double word 0 3 0 2 Step 2 AND the input addressed in this way you will find the execution time in the tables in the chapter entitled List of Instruc tions on page 25 Typical Execution Time in s Direct...

Page 24: ... Load the contents of AR1 and increment them by the offset 23 1 the time required is in the table on page 20 Address is in Execution Time in s AR1 AR2 area crossing 0 00 Step 2 AND link of the input addressed this way see page 25 for the execution time Typical Execution Time in s Direct Addressing Indirect Addressing 0 04 0 05 0 05 Time for A I Total execution time 0 00 s 0 05 s 0 05 s ...

Page 25: ...14 Step 1 Load input I 0 5 addressed via the parameter the time required is in the table on page 20 Address is in Execution Time in s Parameter double word 0 24 Step 2 AND link of the input addressed this way see page 25 for the execution time Typical Execution Time in s Direct Addressing Indirect Addressing 0 06 0 075 0 075 Time for A I Total execution time 0 24 s 0 0 5 s 0 315 s ...

Page 26: ...PUs The descriptions have been kept as concise as possible You will find a detailed functional description in the various STEP 7 reference manuals Please note that in the case of indirect addressing examples see page LEERER MERKER you must add the time required for loading the address of the particular instruction to the execution times listed see page 20 ...

Page 27: ...emory Local data bit Data bit Instance data bit Memory indirect area internal Register ind area internal AR1 Register ind area internal AR2 Area crossing AR1 Area crossing AR2 Via parameter 1 2 1 2 2 2 2 2 2 2 2 2 2 0 1 0 125 0 1 0 125 0 125 0 2 0 2 0 1 0 2 0 125 0 2 0 125 0 2 0 125 0 2 0 125 0 2 0 125 0 2 0 06 0 075 0 06 0 075 0 075 0 12 0 12 0 06 0 12 0 075 0 12 0 075 0 12 0 075 0 12 0 075 0 12 ...

Page 28: ... 125 0 1 0 125 0 125 0 2 0 2 0 1 0 2 0 125 0 2 0 125 0 2 0 125 0 2 0 125 0 2 0 125 0 2 0 06 0 075 0 06 0 075 0 075 0 12 0 12 0 06 0 12 0 075 0 12 0 075 0 12 0 075 0 12 0 075 0 12 0 075 0 12 0 04 0 05 0 04 0 05 0 05 0 08 0 08 0 04 0 08 0 05 0 08 0 05 0 08 0 05 0 08 0 05 0 08 0 05 0 08 0 03 0 042 0 03 0 042 0 042 0 09 0 09 0 03 0 09 0 042 0 09 0 042 0 09 0 042 0 09 0 042 0 09 0 042 0 09 Statusword f...

Page 29: ...ind area internal AR1 Register ind area internal AR2 Area crossing AR1 Area crossing AR2 Via parameter 2 2 2 2 2 2 2 2 2 2 2 0 125 0 125 0 125 0 2 0 2 0 1 0 2 0 125 0 2 0 125 0 2 0 125 0 2 0 125 0 2 0 125 0 2 0 075 0 075 0 075 0 12 0 12 0 06 0 12 0 075 0 12 0 075 0 12 0 075 0 12 0 075 0 12 0 075 0 12 0 05 0 05 0 05 0 08 0 08 0 04 0 08 0 05 0 08 0 05 0 08 0 05 0 08 0 05 0 08 0 05 0 08 0 042 0 042 0...

Page 30: ...and the current RLO the current OR is overwritten with the saved OR In struc Address ID Description Length in Execution Time in s struc tion in Words CPU 412 CPU 414 CPU 416 CPU 417 U AND left parenthesis 1 0 1 0 06 0 04 0 03 UN AND NOT left parenthesis 1 0 1 0 06 0 04 0 03 O OR left parenthesis 1 0 1 0 06 0 04 0 03 ON OR NOT left parenthesis 1 0 1 0 06 0 04 0 03 X Exclusive OR left parenthesis 1 ...

Page 31: ...hetical Expressions continued In struc tion Address ID Description Length in Execution Time in s struc tion in Words CPU 412 CPU 414 CPU 416 CPU 417 Right parenthesis removing an entry from the nesting stack 1 0 1 0 06 0 04 0 03 Statusword for BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Yes Instruction affects Yes 1 Yes 1 ...

Page 32: ...ed according to the rule AND before OR In struc tion Address ID Description Length in Execution Time in s in Words CPU 412 CPU 414 CPU 416 CPU 417 O ORing of AND operations according to the rule AND before OR 1 0 1 0 06 0 04 0 03 Status word for O BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Yes Yes Instruction affects Yes 1 Yes ...

Page 33: ...7 A AN T f T e C f C e AND AND NOT Timer Timer memory indirect addressing Counter Counter memory indirect addressing 1 2 2 1 2 2 0 1 0 125 0 1 0 1 0 125 0 1 0 06 0 075 0 06 0 06 0 075 0 06 0 04 0 05 0 04 0 04 0 05 0 04 0 03 0 042 0 03 0 03 0 042 0 03 Timerpara Counter para Timer counter addressing via param eter 2 0 1 0 1 0 06 0 06 0 04 0 04 0 03 0 03 Status word for A AN BR CC1 CC0 OV OS OR STA R...

Page 34: ... 03 0 03 0 042 0 03 Timerpara Counterpara Timer counter addressing via parame ter 2 0 1 0 1 0 06 0 06 0 04 0 04 0 03 0 03 X XN T f T e C f C e EXCLUSIVE OR EXCLUSIVE OR NOT Timer Timer memory indirect addr Counter Counter mem indirect addr 2 2 2 2 0 125 0 1 0 125 0 1 0 075 0 06 0 075 0 06 0 05 0 04 0 05 0 04 0 042 0 03 0 042 0 03 Timerpara Counterpara EXCLUSIVE OR timer counter address ing via par...

Page 35: ... in ACCU1 and or ACCU1 L In struc Address Description Length in Execution Time in s struc tion Address ID Description Length in Words CPU 412 CPU 414 CPU 416 CPU 417 AW AND ACCU2 L 1 0 1 0 06 0 04 0 03 AW W 16 p AND 16 bit constant 2 0 125 0 075 0 05 0 042 OW OR ACCU2 L 1 0 1 0 06 0 04 0 03 OW W 16 p OR 16 bit constant 2 0 125 0 075 0 05 0 042 XOW EXCLUSIVE OR ACCU2 L 1 0 1 0 06 0 04 0 03 XOW W 16...

Page 36: ... ID Description Length in Words CPU 412 CPU 414 CPU 416 CPU 417 AD AND ACCU2 1 0 1 0 6 0 04 0 3 AD DW 16 p AND 32 bit constant 3 0 185 0 112 0 075 0 062 OD OR ACCU2 1 0 1 0 06 0 04 0 3 OD DW 16 p OR 32 bit constant 3 0 185 0 112 0 075 0 062 XOD EXCLUSIVE OR ACCU2 1 0 1 0 06 0 04 0 03 XOD DW 16 p EXCLUSIVE OR 32 bit constant 3 0 185 0 112 0 075 0 062 Status word for UD OD XOD BR CC1 CC0 OV OS OR ST...

Page 37: ...ich limits the RLO e g a memory instruction that is the FC bit is set to zero Instruc Address Description Length in Execution Time in s Instruc tion Address ID Description Length in Words CPU 412 CPU 414 CPU 416 CPU 417 A AN O ON X XN 0 AND AND NOT OR OR NOT EXCLUSIVE OR EXCLUSIVE OR NOT Result 0 A1 0 and A0 0 1 0 1 0 06 0 04 0 03 0 Result 0 CC1 1 and CC0 0 1 0 1 0 06 0 04 0 03 0 Result 0 CC1 0 an...

Page 38: ...in Execution Time in s Instruc tion Address ID Description Length in Words CPU 412 CPU 414 CPU 416 CPU 417 A AN O ON X XN 0 Result 0 CC1 1 and CC0 0 or CC1 0 and CC0 0 1 0 1 0 06 0 04 0 03 0 Result 0 CC1 0 and CC0 1 or CC1 0 and CC0 0 1 0 1 0 06 0 04 0 03 Status word for A AN O ON X XN BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Yes Yes Yes Yes Yes Instruction affects Yes Yes Yes 1 ...

Page 39: ...me in s CPU 412 CPU 414 CPU 416 CPU 417 A AN O ON X XN UO AND AND NOT OR OR NOT EXCLUSIVE OR EXCLUSIVE OR NOT Unordered math instruction CC1 1 and CC0 1 1 0 1 0 06 0 04 0 03 OS AND OS 1 1 0 1 0 06 0 04 0 03 BR AND BR 1 1 0 1 0 06 0 04 0 03 OV AND OV 1 1 0 1 0 06 0 04 0 03 Status word for A AN O ON X XN BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Yes Yes Yes Yes Yes Yes Yes Yes Instruction...

Page 40: ...iliary edge bit memory 2 2 2 2 2 2 0 2 0 2 0 2 0 3 0 3 0 2 0 3 0 12 0 12 0 12 0 18 0 18 0 12 0 18 0 08 0 08 0 08 0 12 0 12 0 08 0 12 0 06 0 06 0 06 0 12 0 12 0 06 0 12 c d c AR1 m c AR2 m AR1 m AR2 m Parameter 2 2 2 2 2 2 0 2 0 3 0 2 0 3 0 2 0 3 0 2 0 3 0 2 0 3 0 2 0 3 0 12 0 18 0 12 0 18 0 12 0 18 0 12 0 18 0 12 0 18 0 12 0 18 0 08 0 12 0 08 0 12 0 08 0 12 0 08 0 12 0 08 0 12 0 08 0 12 0 06 0 12 ...

Page 41: ... bit Memory indirect area internal Register indirect area internal AR1 Register indirect area internal AR2 Area crossing AR1 Area crossing AR2 Via parameter 1 2 1 2 2 2 2 2 2 2 2 2 2 0 2 0 2 0 2 0 3 0 3 0 2 0 3 0 2 0 3 0 2 0 3 0 2 0 3 0 2 0 3 0 2 0 3 0 12 0 12 0 12 0 18 0 18 0 12 0 18 0 12 0 18 0 12 0 18 0 12 0 18 0 12 0 18 0 12 0 18 0 08 0 08 0 08 0 12 0 12 0 08 0 12 0 08 0 12 0 08 0 12 0 08 0 12...

Page 42: ...ndirect area internal Register indirect area internal AR1 Register indirect area internal AR2 Area crossing AR1 Area crossing AR2 Via parameter 1 2 1 2 2 2 2 2 2 2 2 2 2 0 2 0 2 0 2 0 3 0 3 0 2 0 3 0 2 0 3 0 2 0 3 0 2 0 3 0 2 0 3 0 2 0 3 0 12 0 12 0 12 0 18 0 18 0 12 0 18 0 12 0 18 0 12 0 18 0 12 0 18 0 12 0 18 0 12 0 18 0 08 0 08 0 08 0 12 0 12 0 08 0 12 0 08 0 12 0 08 0 12 0 08 0 12 0 08 0 12 0 ...

Page 43: ...0 06 0 04 0 03 Status word for CLR BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Instruction affects 0 0 0 0 SET Set RLO to 1 1 0 1 0 06 0 04 0 03 Status word for SET BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Instruction affects 0 1 1 0 NOT Negate RLO 1 0 1 0 06 0 04 0 03 Status word for NOT BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Yes Yes Instruction affects 1 Yes SA...

Page 44: ... f T e Start timer as pulse on edge change from 0 to 1 11 2 0 2 0 2 0 12 0 12 0 08 0 08 0 06 0 06 Timer para 2 0 2 0 12 0 08 0 06 SE T f T e Start timer as extended pulse on edge change from 0 to 1 11 2 0 2 0 2 0 12 0 2 0 08 0 08 0 06 0 06 Timer para 2 024 0 12 0 08 0 06 SD T f T e Start timer as ON delay on edge change from 0 to 1 11 2 0 2 0 2 0 12 0 12 0 08 0 08 0 06 0 06 Timer para 2 0 2 01 2 0...

Page 45: ...s CPU 412 CPU 414 CPU 416 CPU 417 SS T f T e Start timer as retentive ON delay on edge change from 0 to 1 11 2 0 2 0 2 0 12 0 12 0 08 0 08 0 06 0 06 Timer para 2 0 2 0 12 0 08 0 06 SF T f T e Start timer as OFF delay on edge change from 0 to 1 11 2 0 2 0 2 0 12 0 12 0 08 0 08 0 06 0 06 Timer para 2 0 2 0 12 0 08 0 06 Status word for SS SF BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Yes In...

Page 46: ...n edge change from 0 to 1 reset edge bit memory for 11 2 0 2 0 2 0 12 0 12 0 08 0 08 0 06 0 06 Timer para reset edge bit memory for starting timer 2 0 2 01 2 0 08 0 06 R T f T e Reset timer 11 2 0 2 0 2 0 12 0 12 0 08 0 08 0 06 0 06 Timer para 2 0 2 0 12 0 08 0 06 Status word for FR R BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Yes Instruction affects 0 0 Plus time required for loading th...

Page 47: ...0 to 1 11 2 0 2 0 4 0 12 0 12 0 08 0 08 0 06 0 06 Counter para 2 0 2 0 12 0 08 0 06 R C f C e Reset counter to 0 when RLO 1 11 2 0 2 0 4 0 12 0 12 0 08 0 08 0 06 0 06 Counter para 2 0 2 0 12 0 08 0 06 CU C f C e Increment counter by 1 on edge change from 0 to 1 11 2 0 2 0 2 0 12 0 12 0 08 0 08 0 06 0 06 Counter para 2 0 2 0 12 0 08 0 06 Status word for S R CU BR CC1 CC0 OV OS OR STA RLO FC Instruc...

Page 48: ...from 0 to 1 11 2 0 2 0 2 0 12 0 2 0 08 0 08 0 06 0 06 FR C f C e Enable counter on edge change from 0 to 1 reset edge bit memory for up and down 11 2 0 2 0 2 0 12 0 12 0 08 0 08 0 06 0 06 Counter para memory for up and down counting and setting the counter 2 0 2 0 12 0 08 0 06 Status word for CD FR BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Yes Instruction affects 0 0 Plus time required ...

Page 49: ...ata byte Instance data byte into ACCU1 2 2 0 2 0 2 0 12 0 12 0 08 0 08 0 09 0 09 g d g AR1 m g AR2 m B AR1 m B AR2 m Parameter Memory indirect area internal 4 Register indirect area internal AR1 4 Register indirect area internal AR2 4 Area crossing AR1 4 Area crossing AR2 4 Via parameter 4 2 2 2 2 2 2 0 1 0 2 0 125 0 2 0 125 0 2 0 125 0 2 0 125 0 2 0 125 0 2 0 06 0 12 0 075 0 12 0 075 0 12 0 075 0...

Page 50: ...5 0 03 0 042 0 042 DBW a DIW a Data word Instance data word into ACCU1 L 2 2 0 2 0 2 0 12 0 12 0 08 0 08 0 09 0 09 h d h AR1 m h AR2 m W AR1 m W AR2 m Parameter Memory indirect area internal4 Register indirect area internal AR1 4 Register indirect area internal AR2 4 Area crossing AR1 4 Area crossing AR2 4 Via parameter 4 2 2 2 2 2 2 0 1 0 2 0 125 0 2 0 125 0 2 0 125 0 2 0 125 0 2 0 125 0 2 0 06 0...

Page 51: ... 05 0 03 0 042 0 042 DBD a DID a Data double word Instance data double word in ACCU1 2 2 0 2 0 2 0 12 0 12 0 08 0 08 0 09 0 09 i d i AR1 m i AR2 m D AR1 m D AR2 m Parameter Memory indirect area internal 4 Register ind area internal AR1 4 Register ind area internal AR2 4 Area crossing AR1 4 Area crossing AR2 4 Via parameter 4 2 2 2 2 2 2 0 1 0 2 0 125 0 2 0 125 0 2 0 125 0 2 0 125 0 2 0 125 0 2 0 0...

Page 52: ...stant into ACCU1 2 2 3 0 125 0 125 0 185 0 075 0 075 0 112 0 05 0 05 0 075 0 042 0 042 0 062 Parameter Load constant into ACCU1 addressed via parameter 2 0 3 0 18 0 12 0 12 L 2 n Load 16 bit binary constant into ACCU1 L 2 0 125 0 075 0 05 0 042 Load 32 bit binary constant into ACCU1 3 0 185 0 112 0 075 0 062 B 16 p Load 8 bit hexadecimal constant into ACCU1 L 1 0 1 0 06 0 04 0 03 L W 16 p Load 16 ...

Page 53: ...0 075 0 062 xxxx Load 4 characters 3 0 185 0 112 0 075 0 062 L D time value Load IEC date 3 0 185 0 112 0 075 0 062 L S5T time value Load S7 time constant 16 bits 2 0 125 0 075 0 05 0 042 L TOD time va lue Load IEC time constant 3 0 185 0 112 0 075 0 062 L T time value Load 16 bit time constant 2 0 125 0 075 0 05 0 042 Load 32 bit time constant 3 0 185 0 112 0 075 0 062 L C count value Load counte...

Page 54: ...ruc Address ID Description Length in Execution Time in s struc tion Address ID Description in Words CPU 412 CPU 414 CPU 416 CPU 417 L P bit pointer Load bit pointer 3 0 185 0 112 0 075 0 062 L L integer Load 32 bit integer constant 3 0 185 0 112 0 075 0 062 L Real number Load floating point number 3 0 185 0 112 0 075 0 062 ...

Page 55: ... 42 0 03 Timer para Load time value addressed via parameter 2 0 1 0 06 0 04 0 03 L C f C e Load count value 11 2 2 0 1 0 12 5 xx 0 06 0 0 75 0 06 0 04 0 0 5 0 04 0 03 0 0 42 0 03 Counter para Load count value addressed via parameter 2 0 1 0 06 0 04 0 03 LC T f T e Load time value in BCD 11 2 2 0 3 0 3 0 18 0 18 0 12 0 12 0 09 0 09 Timer para Load time value in BCD addressed via parameter 2 0 3 0 1...

Page 56: ...a bit memory byte local data byte 13 2 2 0 1 0 125 0 125 0 06 0 075 0 075 0 04 0 05 0 05 0 03 0 042 0 042 DBB a DIB a data byte instance data byte 2 2 0 335 0 335 0 075 0 075 0 05 0 05 0 042 0 042 g d g AR1 m g AR2 m B AR1 m B AR2 m Parameter Memory indirect area internal Register ind area internal AR1 Register ind area internal AR2 Area crossing AR1 Area crossing AR2 Via parameter 2 2 2 2 2 2 0 1...

Page 57: ... 042 MW a LW a bit memory word local data word 13 2 2 0 1 0 125 0 125 0 06 0 075 0 075 0 04 0 05 0 05 0 03 0 042 0 042 DBW a DIW a data word instance data word 2 2 0 335 0 335 0 075 0 075 0 05 0 05 0 042 0 042 h d h AR1 m h AR2 m W AR1 m W AR2 m Parameter Memory indirect area internal Register ind area internal AR1 Register ind area internal AR2 Area crossing AR1 Area crossing AR2 Via parameter 2 ...

Page 58: ... word Local data double word 13 2 2 0 1 0 125 0 125 0 06 0 075 0 075 0 04 0 05 0 05 0 03 0 042 0 042 DBD a DID a Data double word Instance data double word 2 2 0 11 0 11 0 075 0 075 0 05 0 05 0 042 0 042 T i d i AR1 m i AR2 m D AR1 m D AR2 m Parameter Memory indirect area internal Register ind area internal AR1 Register ind area internal AR2 Area crossing AR1 Area crossing AR2 Via parameter 2 2 2 ...

Page 59: ...D a DID a m LD a MD a Load contents from ACCU1 Address register 2 Data double word Instance data double word 32 bit constant as pointer Local data double word Bit memory double word into AR1 1 1 2 2 3 2 2 0 2 0 2 0 3 0 3 0 2 0 2 0 2 0 12 0 12 0 18 0 18 0 12 0 12 0 12 0 08 0 08 0 12 0 12 0 08 0 08 0 08 0 06 0 06 0 12 0 12 0 062 006 006 LAR2 DBD a DID a m LD a MD a Load contents from ACCU1 Data doub...

Page 60: ...14 CPU 416 CPU 417 TAR1 AR2 DBD a DID a LD a MD a Transfer contents from AR1 in ACCU1 Address register 2 Data double word Instance data double word Local data double word Bit memory double word 1 1 2 2 2 2 0 1 0 2 0 125 0 125 0 125 0 125 0 06 0 12 0 075 0 075 0 075 0 075 0 04 0 08 0 05 0 05 0 05 0 05 0 03 0 06 0 042 0 042 0 042 0 042 TAR2 DBD a DID a LD a MD a Transfer contents from AR2 in ACCU1 D...

Page 61: ...ord into ACCU1 0 1 0 06 0 04 0 3 Status word for L STW BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Yes Yes Yes Yes Yes Yes Yes Yes Yes Instruction affects Instruc Address Description Length in Execution Time in s Instruc tion Address ID Description Length in Words CPU 412 CPU 414 CPU 416 CPU 417 T STW Transfer ACCU1 bits 0 to 8 to the status word 0 1 0 06 0 04 0 03 Status word for T STW B...

Page 62: ...U2 The status word is not affected Instruc Address Description Length in Execution Time in s Instruc tion Address ID Description Length in Words CPU 412 CPU 414 CPU 416 CPU 417 L DBNO Load number of data block 1 0 1 0 06 0 04 0 03 L DINO Load number of instance data block 1 0 1 0 06 0 04 0 03 L DBLG Load length of data block into byte 1 0 1 0 06 0 04 0 03 L DILG Load length of instance data block ...

Page 63: ...nd ACCU3 Instruc Address Description Length in Execution Time in s Instruc tion Address ID Description Length in Words CPU 412 CPU 414 CPU 416 CPU 417 I Add 2 integers 16 bits ACCU1 L ACCU1 L ACCU2 L 1 0 1 0 06 0 04 0 03 I Subtract 1 integer from another 16 bits ACCU1 L ACCU2 L ACCU1 L 1 0 1 0 06 0 04 0 03 Status word for I I BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Instruction affects...

Page 64: ...ion Length in Words CPU 412 CPU 414 CPU 416 CPU 417 I Multiply 1 integer by another 16 bits ACCU1 ACCU2 L ACCU1 L 1 0 1 0 06 0 04 0 03 I Divide 1 integer by another 16 bits ACCU1 L ACCU2 L ACCU1 L The remainder is in ACCU1 H 1 0 1 0 24 0 16 0 12 Status word for I I BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Instruction affects Yes Yes Yes Yes ...

Page 65: ...h in Execution Time in s Instruc tion Address ID Description Length in Words CPU 412 CPU 414 CPU 416 CPU 417 D Add 2 integers 32 bit ACCU1 ACCU2 ACCU1 1 0 1 0 06 0 04 0 03 D Subtract 2 integer from another 32 bits ACCU1 ACCU2 ACCU1 1 0 1 0 06 0 04 0 03 D Multiply 2 integer by another 32 bits ACCU1 ACCU2 ACCU1 1 0 1 0 06 0 04 0 03 Status word for D D D D BR CC1 CC0 OV OS OR STA RLO FC Instruction e...

Page 66: ...ength in Words CPU 412 CPU 414 CPU 416 CPU 417 D Divide 2 integer by another 32 bits ACCU1 ACCU2 ACCU1 1 0 6 0 36 0 24 0 18 MOD Divide 2 integer by another 32 bits and load the remainder into ACCU1 ACCU1 remainder of ACCU2 ACCU1 1 0 6 0 36 0 24 0 18 Status word for D MOD BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Instruction affects Yes Yes Yes Yes ...

Page 67: ...scription Length in Words CPU 412 CPU 414 CPU 416 CPU 417 R Add 2 real numbers 32 bits ACCU1 ACCU2 ACCU1 1 0 4 0 24 0 16 0 12 R Subtract 1 real number from another 32 bits ACCU1 ACCU2 ACCU1 1 0 4 0 24 0 16 0 12 R Multiply 1 real number by another 32 bits ACCU1 ACCU2 ACCU1 1 0 2 0 12 0 08 0 06 R Divide 1 real number by another 32 bits ACCU1 ACCU2 ACCU1 1 0 7 0 42 0 28 0 21 Status word for R R R R B...

Page 68: ...on Length in Execution Time in s Instruc tion Address ID Description in Words CPU 412 CPU 414 CPU 416 CPU 417 NEGR Negate the real number in ACCU1 1 0 1 0 06 0 04 0 03 ABS Form the absolute value of the real number in ACCU1 1 0 1 0 06 0 04 0 03 Status word for NEGR ABS BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Instruction affects ...

Page 69: ...upted Instruc Address Description Length in Execution Time in s Instruc tion Address ID Description Length in Words CPU 412 CPU 414 CPU 416 CPU 417 SQRT Calculate the square root of a real number in ACCU1 1 1 7 1 02 0 68 0 51 SQR Form the square of the real number in ACCU1 1 0 2 0 12 0 08 0 06 Status word for SQRT SQR BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Instruction affects Yes Yes...

Page 70: ... Description Length in Execution Time in s Instruc tion Address ID Description Length in Words CPU 412 CPU 414 CPU 416 CPU 417 LN Form the natural logarithm of a real number in ACCU1 1 20 13 9 7 EXP Calculate the exponential value of a real number in ACCU1 to the base e 2 71828 1 21 15 10 8 Status word for LN EXP BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Instruction affects Yes Yes Yes ...

Page 71: ...U 417 SIN Calculate the sine of a real number 1 6 6 3 96 2 64 1 98 ASIN Calculate the arcsine of a real number 1 33 38 22 24 15 17 13 COS Calculate the cosine of a real number 1 6 6 3 96 2 64 1 98 ACOS Calculate the arccosine of a real number 1 36 40 25 27 16 18 12 14 TAN Calculate the tangent of a real number 1 20 14 10 7 ATAN Calculate the arctangent of a real number 1 14 18 10 13 6 9 5 7 Status...

Page 72: ...tatus word is not affected Instruc Address Description Length in Execution Time in s Instruc tion Address ID Description Length in Words CPU 412 CPU 414 CPU 416 CPU 417 i8 Add an 8 bit integer constant 1 0 1 0 06 0 04 0 03 i16 Add a 16 bit integer constant 2 0 125 0 075 0 05 0 042 i32 Add a 32 bit integer constant 3 0 185 0 11 0 075 0 062 ...

Page 73: ...rd is not affected Instruc Address Description Length in Execution Time in s Instruc tion Address ID Description Length in Words CPU 412 CPU 414 CPU 416 CPU 417 AR1 Add the contents of ACCU1 L to those of AR1 1 0 2 0 12 0 08 0 06 AR1 m 0 to 4095 Add a pointer constant to the contents of AR1 2 0 2 0 12 0 08 0 06 AR2 Add the contents of ACCU1 L to those of AR2 1 0 2 0 12 0 08 0 06 AR2 m 0 to 4095 Ad...

Page 74: ...tion Time in s Instruc tion Address ID Description Length in Words CPU 412 CPU 414 CPU 416 CPU 417 I ACCU2 L ACCU1 L 1 0 1 0 06 0 04 0 03 I ACCU2 L0ACCU1 L 1 0 1 0 06 0 04 0 03 I ACCU2 L ACCU1 L 1 0 1 0 06 0 04 0 03 I ACCU2 L ACCU1 L 1 0 1 0 06 0 04 0 03 I ACCU2 L ACCU1 L 1 0 1 0 06 0 04 0 03 I ACCU2 L ACCU1 L 1 0 1 0 06 0 04 0 03 Status word for I I I I I I BR CC1 CC0 OV OS OR STA RLO FC Instruct...

Page 75: ...h in Execution Time in s Instruc tion Address ID Description Length in Words CPU 412 CPU 414 CPU 416 CPU 417 D ACCU2 ACCU1 1 0 1 0 06 0 04 0 03 D ACCU20ACCU1 1 0 1 0 06 0 04 0 03 D ACCU2 ACCU1 1 0 1 0 06 0 04 0 03 D ACCU2 ACCU1 1 0 1 0 06 0 04 0 03 D ACCU2 ACCU1 1 0 1 0 06 0 04 0 03 D ACCU2 ACCU1 1 0 1 0 06 0 04 0 03 Status word for D D D D D D BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates ...

Page 76: ...ngth in Execution Time in s Instruc tion Address ID Description Length in Words CPU 412 CPU 414 CPU 416 CPU 417 R ACCU2 ACCU1 1 0 1 0 06 0 04 0 03 R ACCU20ACCU1 1 0 1 0 06 0 04 0 03 R ACCU2 ACCU1 1 0 1 0 06 0 04 0 03 R ACCU2 ACCU1 1 0 1 0 06 0 04 0 03 R ACCU2 ACCU1 1 0 1 0 06 0 04 0 03 R ACCU2 ACCU1 1 0 1 0 06 0 04 0 03 Status word for R R R R R R BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluat...

Page 77: ...zeros 1 0 1 0 06 0 04 0 03 SLW 0 15 Shift the contents of ACCU1 L to the left Positions that become free are provided with zeros 1 0 1 0 06 0 04 0 03 SLD Shift the contents of ACCU1 to the left Positions that become free are provided with zeros 1 0 1 0 06 0 04 0 03 SLD 0 32 Shift the contents of ACCU1 to the left Positions that become free are provided with zeros 1 0 1 0 06 0 04 0 03 SRW1 Shift th...

Page 78: ...at become free are provided with zeros 1 0 1 0 06 0 04 0 03 SSI1 Shift the contents of ACCU1 L with sign to the right Positions that become free are provided with with the 1 0 1 0 06 0 04 0 03 SSI 0 15 Positions that become free are provided with with the sign bit 15 SSD Shift the contents of ACCU1 with sign to the right Positions that become free are provided with with the 1 0 1 0 06 0 04 0 03 SS...

Page 79: ...st bit shifted is loaded into condition code bit CC1 Instruc Address Description Length in Execution Time in s Instruc tion Address ID Description Length in Words CPU 412 CPU 414 CPU 416 CPU 417 RLD Rotate the contents of ACCU1 to the left 1 0 1 0 06 0 04 0 03 RLD 0 32 the left RRD Rotate the contents of ACCU1 to the right 1 0 1 0 06 0 04 0 03 RRD 0 32 the right Status word for RLD RRD BR CC1 CC0 ...

Page 80: ...n Length in Words CPU 412 CPU 414 CPU 416 CPU 417 RLDA Rotate the contents of ACCU1 one bit position to the left through condition code bit CC 1 0 1 0 06 0 04 0 03 RRDA Rotate the contents of ACCU1 one bit position to the right through condition code bit CC 1 0 1 0 06 0 04 0 03 Status word for RLDA RRDA BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Instruction affects Yes 0 0 ...

Page 81: ... of the bytes in ACCU1 L 1 0 1 0 06 0 04 0 03 CAD Reverse the order of the bytes in ACCU1 1 0 1 0 06 0 04 0 03 TAK Swap the contents of ACCU1 and ACCU2 1 0 1 0 06 0 04 0 03 ENT The contents of ACCU2 and ACCU3 are transferred to ACCU3 and ACCU4 1 0 1 0 06 0 04 0 03 LEAVE The contents of ACCU3 and ACCU4 are transferred to ACCU2 and ACCU3 1 0 1 0 06 0 04 0 03 PUSH The contents of ACCU1 ACCU2 and ACCU...

Page 82: ... 01 Accumulator Transfer Instructions Incrementing and Decrementing continued Instruc Address Description Length in Execution Time in s Instruc tion Address ID Description Length in Words CPU 412 CPU 414 CPU 416 CPU 417 INC k8 Increment ACCU1 LL 1 0 1 0 06 0 04 0 03 DEC k8 Decrement ACCU1 LL 1 0 1 0 06 0 04 0 03 ...

Page 83: ...The status word is not affected Instruc Address Description Length in Execution Time in s Instruc tion Address ID Description Length in Words CPU 412 CPU 414 CPU 416 CPU 417 BLD k8 Program display instruction Is treated by the CPU as a null operation instruction 1 0 1 0 06 0 04 0 03 NOP 0 1 Null operation instruction 1 0 1 0 06 0 04 0 03 ...

Page 84: ...from BCD 0 to 999 to integer 16 bits BCD To Int 1 0 1 0 06 0 04 0 03 BTD Convert contents of ACCU1 from BCD 0 to 9 999 999 to double integer 32 bits BCD To Doubleint 1 0 1 0 06 0 04 0 03 DTR Convert contents of ACCU1 from double integer 32 bits to real number 32 bits Doubleint To Real 1 0 3 0 18 0 12 0 09 ITD Convert contents of ACCU1 from integer 16 bits to double integer 32 bits Int To Doubleint...

Page 85: ...D Description Length in Words CPU 412 CPU 414 CPU 416 CPU 417 ITB Convert contents of ACCU1 L from integer 16 bits to BCD from 0 to 999 Int To BCD 1 0 1 0 06 0 04 0 03 DTB Convert contents of ACCU1 from double integer 32 bits to BCD from 0 to 9 999 999 Doubleint To BCD 1 0 2 0 12 0 08 0 06 Status word for ITB DTB BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Instruction affects Yes Yes ...

Page 86: ... number into a 32 bit integer The number is rounded up to the next whole number 1 0 4 0 24 0 16 0 12 RND Convert a real number into a 32 bit integer 1 0 4 0 24 0 16 0 12 RND Convert a real number into a 32 bit integer The number is rounded down to the next whole number 1 0 4 0 24 0 16 0 12 TRUNC Convert a real number into a 32 bit integer The places after the decimal point are truncated 1 0 4 0 24...

Page 87: ... the ones complement of ACCU1 L 1 0 1 0 06 0 04 0 03 INVD Form the ones complement of ACCU1 1 0 1 0 06 0 04 0 03 Status word for INVI INVD BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Instruction affects NEGI Form the twos complement of ACCU1 L integer 1 0 1 0 06 0 04 0 03 NEGD Form the twos complement of ACCU1 double integer 1 0 1 0 06 0 04 0 03 Status word for NEGI NEGD BR CC1 CC0 OV OS ...

Page 88: ...PU 414 CPU 416 CPU 417 CALL FB q DB q Unconditional call of an FB with parameter transfer 15 171 4 0 3 2 4 3 1 6 3 1 26 3 CALL SFB q DB q Unconditional call of an SFB with parameter transfer 16 171 4 0 3 2 4 3 1 6 3 1 26 3 CALL FC q Unconditional call of a function with parameter transfer 7 81 3 2 3 1 92 3 1 28 3 1 02 3 CALL SFC q Unconditional call of an SFC with parameter transfer 8 3 2 3 1 92 3...

Page 89: ... 72 0 72 0 72 CC FB q FC q FB e FC e Parameter Conditional call of blocks without parameter transfer Memory indirect FB call Memory indirect FC call FB FC call via parameter 11 2 2 2 2 2 2 0 5 4 2 2 0 5 4 2 2 0 5 4 2 2 0 5 4 2 2 0 5 4 1 32 0 3 4 1 32 0 3 4 1 32 0 3 4 1 32 0 3 4 1 32 0 3 4 0 88 0 2 4 0 88 0 2 4 0 88 0 2 4 0 88 0 2 4 0 88 0 2 4 0 72 0 18 4 0 72 0 18 4 0 72 0 18 4 0 72 0 18 4 0 72 0 ...

Page 90: ... 1 1 2 0 5 0 125 2 0 5 0 1 1 2 0 5 0 125 2 0 5 0 1 1 2 0 5 0 125 2 0 5 0 061 2 0 3 0 0752 0 3 0 061 2 0 3 0 0752 0 3 0 06 1 2 0 3 0 075 2 0 3 0 06 1 2 0 3 0 075 2 0 3 0 06 1 2 0 3 0 075 2 0 3 0 041 2 0 2 0 052 0 2 0 041 2 0 2 0 052 0 2 0 04 1 2 0 2 0 05 2 0 2 0 04 1 2 0 2 0 05 2 0 2 0 04 1 2 0 2 0 05 2 0 2 0 031 2 0 21 0 0422 0 21 0 031 2 0 21 0 0422 0 21 0 03 1 2 0 21 0 042 2 0 21 0 03 1 2 0 21 0...

Page 91: ...4 CPU 416 CPU 417 BE End block 1 4 0 2 4 1 6 1 62 BEU End block unconditionally 1 4 0 2 4 1 6 1 62 Status word for BE BEU BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Instruction affects 0 0 1 0 BEC End block conditionally if RLO 1 4 2 0 51 2 52 0 31 1 78 0 21 1 68 0 181 Status word for BEC BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Yes Instruction affects Yes 0 1 1 0 1 If jump i...

Page 92: ...he two current data blocks The current shared data block becomes the current instance data block and vice versa The sta tus word is not affected Instruc Address Description Length in Execution Time in s Instruc tion Address ID Description Length in Words CPU 412 CPU 414 CPU 416 CPU 417 CDB Exchange shared data block and instance data block 1 0 2 0 12 0 08 0 06 ...

Page 93: ... CPU 416 CPU 417 JU LABEL Jump unconditionally 2 0 6 0 36 0 24 0 21 Status word for JU BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Instruction affects JC LABEL Jump if RLO 1 2 0 6 0 1252 0 36 0 0752 0 24 0 052 0 21 0 0422 JCN LABEL Jump if RLO 0 2 0 6 0 125 2 0 36 0 075 2 0 24 0 05 2 0 21 0 042 2 Status word for JC JCN BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Yes Instruction a...

Page 94: ...05 2 0 21 0 042 2 JNB LABEL Jump if RLO 0 Save the RLO in the BR bit 2 0 6 0 125 2 0 36 0 075 2 0 24 0 05 2 0 21 0 042 2 Status word for JCB JNB BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Yes Instruction affects Yes 0 1 1 0 JBI LABEL Jump if BR 1 2 0 6 0 125 2 0 36 0 075 2 0 24 0 05 2 0 21 0 042 2 JNBI LABEL Jump if BR 0 2 0 6 0 125 2 0 36 0 075 2 0 24 0 05 2 0 21 0 042 2 Status word for...

Page 95: ...4 CPU 416 CPU 417 JO LABEL Jump on stored overflow OV 1 2 0 6 0 1252 0 36 0 0752 0 24 0 052 0 21 0 0422 Status word for JO BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Yes Instruction affects JOS LABEL Jump on stored overflow OS 1 2 0 6 0 125 2 0 36 0 075 2 0 24 0 05 2 0 21 0 042 2 Status word for JOS BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Yes Instruction affects 0 2 If jump ...

Page 96: ... 042 2 JZ LABEL Jump if result 0 CC1 0 and CC0 0 2 0 6 0 125 2 0 36 0 075 2 0 24 0 05 2 0 24 0 05 2 JP LABEL Jump if result 0 CC1 1 and CC0 0 2 0 6 0 125 2 0 36 0 075 2 0 24 0 05 2 0 24 0 05 2 JM LABEL Jump if result 0 CC1 0 and CC0 1 2 0 6 0 125 2 0 36 0 075 2 0 24 0 05 2 0 24 0 05 2 JN LABEL Jump if result 0 0 CC1 1 and CC0 0 or CC1 0 and CC0 1 2 0 6 0 125 2 0 36 0 075 2 0 24 0 05 2 0 24 0 05 2 ...

Page 97: ... 416 CPU 417 JMZ LABEL Jump if result v 0 CC1 0 and CC0 1 or CC1 0 and CC0 0 2 0 6 0 125 2 0 36 0 075 2 0 24 0 05 2 0 21 0 042 2 JPZ LABEL Jump if result w 0 CC1 1 and CC0 0 or CC1 0 and CC0 0 2 0 6 0 125 2 0 36 0 075 2 0 24 0 05 2 0 21 0 042 2 Status word for JUO JZ JP JM JN JMZ JPZ BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Yes Yes Instruction affects 2 If jump is not executed ...

Page 98: ...list of jump instructions The address identifier is a jump label to subsequent instructions in this list ACCU1 LL contains the number of the jump instruction to be executed max 254 The number of the first jump instruction is 0 2 0 7 0 42 0 28 0 24 LOOP LABEL Decrement ACCU1 L and jump if ACCU1 L 0 0 loop programming 2 0 6 0 125 1 0 36 0 075 1 0 24 0 05 1 0 21 0 042 1 Status word for JL LOOP BR CC1...

Page 99: ...ents unchanged Instruc Address ID Description Length in Execution Time in s Instruc tion Address ID Description Length in Words CPU 412 CPU 414 CPU 416 CPU 417 MCR Open an MCR zone Save the RLO to the MCR stack 1 0 1 0 06 0 04 0 03 Status word for MCR CC1 BR CC0 OV OS OR STA RLO FC Instruction evaluates Yes Instruction affects 0 1 0 MCR Close an MCR zone Pop an entry off the MCR stack 1 0 1 0 06 0...

Page 100: ...ontinued Instruc Address Description Length in Execution Time in s Instruc tion Address ID Description Length in Words CPU 412 CPU 414 CPU 416 CPU 417 MCRA Activate the MCR 1 0 1 0 06 0 04 0 03 MCRD Deactivate the MCR 1 0 1 0 06 0 04 0 03 Status word for MCRA MCRD BR CC1 CC0 OV OS OR STA RLO FC Instruction evaluates Instruction affects ...

Page 101: ...system is different for each of the S7 400 CPUs You will find a detailed description of the OBs and their use in the STEP 7 Programming Manual Organization Blocks CPU 412 CPU 414 CPU 414 4H CPU 416 CPU 417 CPU 417 4H Start Events Hexadecimal Values Free cycle OB 1 x x x x x x 1101 1102 1103 1104 1105 Time of day interrupts OB 10 x x x x x x 1111 OB 11 x x x x x x 1112 OB 12 x x x x x 1113 OB 13 x ...

Page 102: ...nts Hexadecimal Values Time delay interrupts OB 20 x x x x x x 1121 OB 21 x x x x x x 1122 OB 22 x x x x x 1123 OB 23 x x x x x 1124 Timed interrupts 1 OB 30 x x x 1131 OB 31 x x x 1132 OB 32 x x x x x x 1133 OB 33 x x x x x 1134 OB 34 x x x x x 1135 OB 35 x x x x x x 1136 OB 36 x x x 1137 OB 37 x x x 1138 OB 38 x x x 1139 1 Further start events of H CPUs for OB 30 to OB 38 1130H ...

Page 103: ...terrupts OB 40 x x x x x x 1141 1142 1143 1144 1145 OB 41 x x x x x x 1141 1142 1143 1144 1145 OB 42 x x x x x 1141 1142 1143 1144 1145 OB 43 x x x x x 1141 1142 1143 1144 1145 OB 44 x x x 1141 1142 1143 1144 1145 OB 45 x x x 1141 1142 1143 1144 1145 OB 46 x x x 1141 1142 1143 1144 1145 OB 47 x x x 1141 1142 1143 1144 1145 Interrupt OBs for DPV1 OB 55 x x x x x x 1155 OB 56 x x x x x x 1156 OB 57 ...

Page 104: ...x x x x 1164 OB 62 x x x x x x 1165 OB 63 x x x x x x 1166 OB 64 x x x x x x 1167 Redundancy error interrupts OB 70 x x 73A2 73A3 72A3 OB 72 x x 7301 7302 7303 7320 7321 7322 7323 7331 7333 7334 7335 7340 7341 7342 7343 7344 7950 7951 7952 7852 7953 7954 7955 7855 7956 73C1 73C2 Asynchronous error interrupts OB 80 x x x x x x 3501 3502 3505 3506 3507 350A OB 81 x x x x x x 3821 3822 3823 3825 3826...

Page 105: ... 39C51 OB 87 x x x x x x 35D2 35D3 35D4 35D5 35E1 35E2 35E3 35E4 35E5 35E6 OB 88 x x x x x x 3571 3572 3573 3574 3575 3576 3578 357A Background OB 90 x x x x 1191 1192 1193 1195 Warm restart 1 OB 100 x x x x x x 1381 1382 138A 138B Hot restart OB 101 x x x x 1383 1384 Cold restart OB 102 x x x x x x 1385 1386 1387 1388 Synchronous error interrupts OB 121 x x x x x x 2521 2522 2523 2524 2525 2526 2...

Page 106: ... sizes of the function blocks you can create for the various S7 400 CPUs Function Blocks CPU 412 1 CPU 412 2 CPU 414 CPU 416 CPU 417 Quantity 256 256 1024 2048 6144 Permissible numbers 0 to 255 0 to 255 0 to 1023 0 to 2047 0 to 6143 Maximum size of a function block code required for execution 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes ...

Page 107: ...414 CPU 416 CPU 417 Quantity 256 256 2048 2048 6144 Permissible numbers 0 to 255 0 to 255 0 to 2047 0 to 2047 0 to 6143 Maximum size of a function code required for execution 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes Data Blocks CPU 412 1 CPU 412 2 CPU 414 CPU 416 CPU 417 Quantity 511 511 4095 4095 8191 Permissible numbers 1 to 511 1 to 511 1 to 4095 1 to 4095 1 to 8191 Maximum size of a d...

Page 108: ...PU 414 4H 417 4H solo CPU 414 4H 417 4H redun dant 0 SET_CLK Set clock 195 111 75 66 xx xx 1 READ_CLK Read clock 31 18 13 10 xx xx 2 SET_RTM Set run time meter 27 16 11 9 xx xx 3 CTRL_RTM Start and stop run time meter 23 14 10 8 xx xx 4 READ_RTM Read run time meter 29 18 12 10 xx xx 5 GADR_LGC Find logical address of a channel Rack 0 38 23 15 13 xx xx internal DP 51 31 21 18 xx xx 6 RD_SINFO Read ...

Page 109: ...U 417 CPU 414 4H 417 4H solo CPU 414 4H 417 4H redun dant 9 EN_MSG Enable block related symbol related and group status messages First call REQ 1 182 103 69 59 xx xx Last call 41 24 16 13 xx xx 10 DIS_MSG Disable block related symbol related and group status messages First call REQ 1 183 104 70 60 xx xx Last call 41 24 16 13 xx xx ...

Page 110: ...ternal DP interface REQ 1 158 90 60 52 Intermediate call internal DP interface BUSY 1 1 40 n 4 23 n 3 16 n 2 13 n 2 Last call internal DP interface BUSY 0 1 42 n 4 24 n 3 17 n 2 14 n 2 11 DPSYC_FR First call external DP interface REQ 1 76 51 40 36 Intermediate call external DP interface BUSY 1 1 56 n 4 35 n 3 26 n 2 52 n 2 Last call external DP interface BUSY 0 1 56 n 4 35 n 3 26 n 2 23 n 2 1 n nu...

Page 111: ...ves via integrated DP interface MODE 1 First call 265 149 102 89 Intermediate call 81 48 33 28 Last call 103 61 41 36 12 D_ACT_DP Deactivate and activate DP slaves via integrated DP interface MODE 2 First call 485 290 193 170 Intermediate call 81 48 32 28 Last call 101 60 40 35 12 D_ACT_DP Deactivate and activate DP slaves via external DP interface MODE 0 86 51 34 29 12 D_ACT_DP Deactivate and act...

Page 112: ...4H 417 4H solo CPU 414 4H 417 4H redun dant 12 D_ACT_DP Deactivate and activate DP slaves via external DP interface MODE 2 First call 472 280 186 169 Intermediate call 80 48 32 28 Last call 101 60 41 35 13 DP_NRMDG Read slave diagnostic data First call 240 141 95 83 xx xx Intermediate call 88 53 36 30 xx xx Last call 28 bytes 122 72 48 42 xx xx ...

Page 113: ...bytes via integrated DP interface 3 bytes 601 622 361 372 251 252 211 212 xx1 xx2 xx1 xx2 via integrated DP interface 32 bytes 641 662 371 412 251 262 211 222 xx1 xx2 xx1 xx2 via external DP interface 3 bytes 661 682 421 432 301 312 271 272 xx1 xx2 xx1 xx2 via external DP interface 32 bytes 1251 1282 961 982 831 852 791 802 xx1 xx2 xx1 xx2 17 ALARM_SQ Generate acknowledgeable block related message...

Page 114: ...014 xx n yy xx n yy Source Load memory 522 n 0 45 380 n 0 3 317 n 0 27 301 n 0 25 xx n yy xx n yy 21 FILL Set array default variables within the work memory n length of target variables in bytes 43 n 0 024 26 n 0 016 17 n 0 012 13 n 0 01 xx n yy xx n yy 22 CREAT_DB Create data block n DB length bytes 111 65 43 38 xx n yy xx n yy Occupy last free DB No from a field of 100 DBs 517 294 196 164 xx xx ...

Page 115: ...O 8 13Bit 62 46 39 36 xx xx 28 SET_TINT Set time of day interrupt 92 54 36 32 xx xx 29 CAN_TINT Cancel time of day interrupt 30 17 12 10 xx xx 30 ACT_TINT Activate time of day interrupt 63 35 24 21 xx xx 31 QRY_TINT Query time of day interrupt 16 10 7 5 xx xx 32 SRT_DINT Start time delay interrupt 49 28 19 17 xx xx 33 CAN_DINT Cancel time delay interrupt 33 19 13 11 xx xx 34 QRY_DINT Query time de...

Page 116: ...xx xx xx 40 EN_IRT Stop discarding events Enable all events MODE 0 205 121 82 71 xx xx Enable all events in a priority class MODE 1 54 30 20 17 xx xx xx xx Enable an event MODE 2 29 17 12 10 xx xx xx xx 41 DIS_AIRT Delay interrupt events the first time delay is activated1 215 129 86 77 xx xx if the delay is already activated 18 10 8 6 xx xx 1 When activating the delay for the first time the SFC 41...

Page 117: ...bstitute value to ACCU1 22 13 9 7 xx xx 46 STP Force CPU into STOP mode cannot be measured 47 WAIT Delay program execution in addition to waiting time 15 8 7 5 xx xx xx xx 48 SNC_RTCB Synchronize slave clocks 19 12 8 7 xx xx 49 LGC_GADR Find slot with logical address 40 25 17 14 xx xx 50 RD_LGADR Find all logical addresses of a block run time entry for 1 DI 32 in the central rack 103 61 41 34 xx x...

Page 118: ...n dant 51 RDSYSST Module identification partial list Display one data record 0111 125 79 51 46 xx xx 51 RDSYSST Module Identification partial list Display all data records 0012 256 154 102 89 xx xx Display one data record 0112 156 94 62 55 xx xx xx xx Display header information 0F12 111 66 43 39 xx xx 51 RDSYSST Save partial list Display header information 0F13 135 90 56 153 xx xx ...

Page 119: ... 57 51 xx x 51 RDSYSST Status of Module LEDs partial list Display status of all LEDs 0019 264 157 121 108 xx Display header information 0F19 182 113 80 69 xx 51 RDSYSST Component Identification partial list Display all components 001C 199 118 77 70 xx xx Display one of the components 011C 136 84 56 49 xx xx xx xx Display all components of a H system CPU 021C xx xx xx xx Display a component of all ...

Page 120: ...ng OB 0125 121 78 51 45 xx xx 51 RDSYSST Assignment between an OB and corresponding process image partitions 0225 106 106 106 95 xx xx Auslesen der Kopfinfo 0F25 118 70 46 41 xx xx 51 RDSYSST Status information communication partial list Display status information of a communication unit 0132 165 291 97 174 64 116 57 102 xx xx 51 RDSYSST Status information communication partial list Display status...

Page 121: ... CPU 412 CPU 414 CPU 416 CPU 417 CPU 414 4H 417 4H solo CPU 414 4H 417 4H redun dant 51 RDSYSST Modules LEDs partial list Status of an LED 0174 182 124 88 77 xx xx xx xx 51 RDSYSST Switched DP slaves in the H system partial list Communication status between the H system and a switched DP slave 0C75 xx xx ...

Page 122: ...formation partial list Display status information of all inserted modules n number of DR 0091 561 n 22 329 n 19 218 n 16 180 n 14 Display status information of all modules racks with incorrect type indentification 0191 546 n 70 381 n 60 230 n 40 220 n 35 All faulty modules 0291 515 n 99 371 n 22 246 n 18 213 n 18 All unavailable modules 0391 517 n 69 376 n 60 249 n 40 216 n 35 All submodules of th...

Page 123: ...h logical basic address 0C91 236 150 99 87 xx xx 51 RDSYSST Module status information partial list of a module distributed with logical basic address 4C91 First call 116 95 63 55 xx xx Module status information partial list of a module distributed with logical basis address 4C91 Intermediate call xx xx Module status information partial list of a module distributed with logical basic address 4C91 L...

Page 124: ... n 16 118 n 10 88 n 8 xx n yy xx n yy Distributed all modules in the specified DP station 0D91 235 274 138 161 91 107 80 94 xx xx xx all assigned modules 0E91 854 505 335 289 51 RDSYSST Rack station status information partial list central Display setpoint status of rack 0 0092 128 87 57 51 xx xx distributed Display setpoint status of DP system 1 0092 694 387 257 219 xx xx 51 RDSYSST Display setpoi...

Page 125: ...atus of rack 0 0292 129 87 57 51 xx xx distributed Display the actual status of DP system 1 0292 677 417 277 239 xx xx 51 RDSYSST Display the actual status of the stations of a DP master system via external DP interface 4292 250 147 97 86 xx xx 51 RDSYSST Display the status of rack 0 battery buffer if at least one battery has failed 0392 144 87 57 51 xx xx 51 RDSYSST Display the status of the enti...

Page 126: ...ibuted Display the diagnostic status of the DP system 1 stations via integrated DP interface 0692 811 487 323 273 xx xx 51 RDSYSST Diagnostic status of the stations of a DP master system connected via an external DP interface 4692 First call 252 148 97 87 xx xx Intermediate call 140 84 55 49 Last call 157 94 62 55 51 RDSYSST Advanced DP master system information partial list Display advanced infor...

Page 127: ...erating mode max 21 00A0 135 314 86 188 60 125 45 111 xx xx xx xx Display the latest entries n 1 23 01A0 135 n 7 8 86 n 4 4 57 n 3 50 n 3 xx n yy xx n yy Display the header information 0FA0 115 75 49 43 xx xx 51 RDSYSST Diagnostic data DS 0 partial list Display via logical basic address 00B1 Central 342 212 148 133 xx xx 51 RDSYSST Distributed 00B1 first call 313 184 123 109 xx xx Distributed 00B1...

Page 128: ...ata DR 1 partial list Display via physical address 00B2 Display a 16 byte long DR 1 247 147 100 89 xx xx 51 RDSYSST Diagnostic data DR 1 partial list Display via logical basic address 00B3 Display a 16 byte long DR 1 central 383 245 178 162 xx xx distributed first call 00B3 312 183 122 108 xx xx distributed intermediate call 00B3 173 102 68 59 xx xx distributed last call 00B3 214 127 84 74 xx xx D...

Page 129: ... REQ 0 00B4 115 149 148 Last call 6 240 bytes 00B4 246 170 135 170 174 173 52 WR_USMSG Write user entry in diagnostic buffer write with message 151 93 66 54 xx xx without message 87 53 36 3030 xx xx 54 RD_DPARAM Read dynamic parameters local AI 8 13 bits 154 85 57 50 xx xx distributed AI 8 12 bits DS1 14 bytes 167 101 68 59 xx xx 55 WR_PARM Write dynamic parameters local AI 8 13 bits 359 228 164 1...

Page 130: ...efined dynamic parameters AI 8 13 bits local 404 272 203 184 xx xx distributed First call AI 8 12 bits 2 240 bytes 248 146 98 85 xx xx Intermediate last call 121 72 48 41 xx xx 57 PARM_MOD Assign module parameters local Module DS number DS lengths in bytes AI 8 13 bits 695 459 349 318 xx xx distributed AO 8 12 bits First call 16 240 bytes 245 144 97 84 xx xx distributed Intermediate last call 118 ...

Page 131: ...n yy First call integrated DP interface module n number of bytes 283 n 0 1 168 n 0 04 113 n 0 03 97 n 0 03 xx n yy xx n yy Intermediate call REQ 0 integrated DP interface module 112 66 45 38 xx xx Last call integrated DP interface module 114 67 45 38 xx xx First call external DP interface module n number of bytes 277 n 0 06 163 n 0 06 109 n 0 04 96 n 0 03 xx n yy xx n yy Intermediate call REQ 0 ex...

Page 132: ...Intermediate call REQ 0 integrated DP interface module 112 66 45 38 xx xx Last call integrated DP interface module n number of bytes 201 n 0 04 119 n 0 04 81 n 0 03 70 n 0 03 xx n yy xx n yy First call external DP interface module 255 151 101 88 xx xx Intermediate call REQ 0 external DP interface module 113 67 45 40 xx xx Last call external DP interface module n number of bytes 196 n 0 06 116 n 0 ...

Page 133: ...munication SFB instance 104 63 44 35 xx xx 64 TIME_TCK Display millisecond timer 19 11 8 6 xx xx 65 X_SEND Transmit data to external partner First call establish a connection 1 76 bytes REQ 1 641 458 412 355 First call connection present 1 76 bytes 509 293 195 168 Intermediate call 1 76 bytes 150 87 58 49 Last call BUSY 0 254 150 100 87 66 X_RCV Receive data from external partner Test reception 1 ...

Page 134: ...rst call establish a connection 1 76 bytes REQ 1 572 416 384 332 First call connection present 1 76 bytes 444 252 167 144 Intermediate call 1 76 bytes 153 89 60 50 Last call BUSY 0 364 214 142 123 68 X_PUT Write data to external partner First call establish a connection 1 76 bytes REQ 1 651 462 415 357 First call connection present 1 76 bytes 519 297 198 170 Intermediate call 1 76 bytes 155 89 60 ...

Page 135: ...Y 0 228 219 254 219 72 I_GET Read data from internal partner First call establish a connection 1 76 bytes REQ 1 732 442 401 346 First call connection present 1 76 bytes 425 225 170 153 Intermediate call 1 76 bytes 175 93 62 53 Last call BUSY 0 407 218 145 126 73 I_PUT Write data to internal partner First call establish a connection 1 76 bytes REQ 1 539 843 304 486 204 431 172 372 First call connec...

Page 136: ...ber of bits to set at 1 31 n 0 25 20 n 0 2 14 n 0 2 11 n 0 2 xx n yy xx n yy 80 RSET 1 Delete bit array in I O area n number of bits to set at 0 31 n 0 25 19 n 0 2 14 n 0 2 11 n 0 2 xx n yy xx n yy 81 UBLKMOV Copy variable without interruption n number of bytes to copy 39 n 0 08 23 n 0 05 16 n 0 03 12 n 0 03 xx n yy xx n yy 87 C_DIAG Determine current connection status MODE 0 28 17 12 9 xx xx Mode...

Page 137: ...2 112 75 66 xx xx MODE 2 109 62 41 36 xx xx MODE 3 189 115 75 69 xx xx 103 DP_TOPOL Detemine bus topology in a DP master system first call REQ 1 272 160 109 96 xx xx Intermediate call 46 27 19 16 xx xx Last call BUSY 0 49 28 20 17 xx xx 104 CIR Controls the CiR procedure MODE 0 information 19 11 8 6 xx MODE 1 Enable CiR procedure 19 11 8 6 xx MODE 2 Disable CiR procefure entirely 19 11 8 6 xx MODE...

Page 138: ...xx 0 MODE 1 161 14551 93 1185 1 62 1535 1 53 1392 1 xx xx 1 xx xx 1 MODE 2 161 1273 1 94 1026 1 63 1322 1 53 1201 1 xx xx 1 xx xx 1 MODE 3 163 1459 2 94 1179 2 63 1526 2 54 1390 2 xx xx 2 xx xx 2 0 Depending on the size of the SYS_INST target area and on the number of the system resources to be read 1 Depending on the number of active messages assigned system resources 2 Depending on the number of...

Page 139: ...23 1 xx xx 1 xx xx 1 MODE 2 201 970 1 113 824 1 76 1035 1 67 925 1 xx xx 1 xx xx 1 MODE 3 198 1012 2 112 826 2 75 1043 2 65 927 2 xx xx 2 xx xx 2 107 ALARM_DQ Acknowledgeable block related messages create first call SIG 0 1 285 170 120 101 xx xx Call without message 133 79 53 44 xx xx 1 Depending on the number of active messages assigned system resources 2 Depending on the number of active message...

Page 140: ...PUs 414 4H 417 4H redun dant 108 ALARM_D Not acknowledgeable block related messages create first call SIG 0 1 273 163 108 91 xx xx Call without message 122 71 47 39 xx xx 126 SYNC_PI Update the process image partition of the inputs in a synchronous cycle 61 37 25 21 127 SYNC_PO Update the process image partition of the outputs in a synchronous cycle 60 36 24 20 ...

Page 141: ...e in s SFC No SFC Name Function CPU 412 CPU 414 CPU 416 CPU 417 CPUs 414 4H 417 4H solo CPUs 414 4H 417 4H redun dant 0 CTU Count up 4 3 1 1 xx xx 1 CTD Count down 4 2 1 1 xx xx 2 CTUD Count up and down 4 2 1 1 xx xx 3 TP Generate pulse 26 15 10 8 xx xx 4 TON Generate on delay 25 15 10 8 xx xx 5 TOF Generate off delay 19 11 7 6 xx xx 8 USEND Send data without coordination one send parameter suppli...

Page 142: ...rameter supplied JOB activated 136 77 50 44 xx xx JOB checked 133 78 50 43 xx xx JOB finished NDR 1 1 440 bytes 280 316 165 186 108 121 92 106 xx xx xx xx 12 BSEND Send data block by block JOB activated 1 3000 bytes 386 220 148 129 xx xx JOB checked 164 95 63 54 xx xx JOB finished DONE 1 161 92 62 54 xx xx 13 BRCV Receive data block by block JOB activated 1 3000 bytes 187 108 71 62 xx xx JOB check...

Page 143: ...335 186 129 113 xx xx JOB checked 149 86 57 49 xx xx JOB finished NDR 1 1 450 bytes 282 316 163 183 108 121 92 106 xx xx xx xx 15 PUT Write data to remote CPU JOB activated 1 404 bytes 445 478 257 277 173 180 147 160 xx xx xx xx JOB checked 149 86 57 49 xx xx JOB finished DONE 1 147 85 56 48 xx xx 16 PRINT Send data to a printer JOB activated REQ 1 462 502 260 284 174 186 150 162 xx xx xx xx JOB c...

Page 144: ... 60 52 xx xx JOB finished DONE 1 153 89 59 51 xx xx 20 STOP Stop remote device JOB activated REQ 1 411 242 157 136 xx xx JOB checked 156 90 59 51 xx xx JOB finished DONE 1 153 89 58 51 xx xx 21 RESUME Restart remote device JOB activated REQ 1 434 246 159 142 xx xx JOB checked 157 90 59 52 xx xx JOB finished DONE 1 153 90 59 52 xx xx 22 STATUS Query status of remote partner JOB activated REQ 1 279 ...

Page 145: ...50 43 xx xx JOB finished 462 266 176 150 xx xx 31 NOTIFY_8P Generate block related message without acknowledgment JOB activated SIG 0 1 1 420 bytes 543 588 309 331 207 220 178 191 xx xx xx xx JOB checked 206 118 78 67 xx xx JOB finished DONE 1 215 123 81 70 xx xx 32 DRUM Implement sequencer 39 21 14 13 xx xx 33 ALARM Generate block related message with acknowledgment JOB activated SIG 0 1 1 420 by...

Page 146: ...144 xx xx JOB checked 206 118 78 68 xx xx JOB finished DONE 1 213 121 80 70 xx xx 35 ALARM_8P Generate block related message with accompanying values for 8 signals JOB activated SIG 0 1 1 420 bytes 549 582 306 326 209 222 182 190 xx xx xx xx JOB checked 205 118 78 68 xx xx JOB finished DONE 1 213 122 81 70 xx xx 36 NOTIFY Generate block related message without acknowledgment JOB activated SIG 0 1 ...

Page 147: ...ytes 372 215 145 127 xx xx JOB checked 160 92 62 54 xx xx JOB finished DONE 1 160 91 61 54 xx xx 52 RDREC Read data record from a DP slave via integrated DP interface First call 2 16 bytes 289 167 111 97 xx xx Intermediate call 128 74 49 43 xx xx Last call 221 127 86 76 xx xx 52 RDREC Read data record from a DP slave via external DP interface First call 4 16 bytes 291 167 108 94 xx xx Intermediate...

Page 148: ...0 76 50 43 xx xx Last call 132 77 51 45 xx xx 53 WRREC Write data record in a DP slave via external DP interface First call 2 14 bytes 312 176 116 101 xx xx Intermediate call 130 76 50 43 xx xx Last call 134 77 51 45 xx xx 54 RALRM Receive interrupt from a DP slave Runtime measurement for non I O dependent OBs MODE 1 OB 1 118 73 48 42 xx xx 54 RALRM Receive interrupt from a DP slave Runtime measur...

Page 149: ...PU 414 CPU 412 Function SFB Name 54 RALRM Receive interrupt from a DP slave Runtime measurement at external DP interface MODE 1 OB 40 OB 83 OB 86 404 239 156 137 xx xx OB 55 to OB 57 OB 82 675 431 281 246 xx xx OB 70 xx xx 54 RALRM Receive interrupt from a DP slave Runtime measurement at central I O MODE 1 OB 40 OB 82 OB 83 OB 86 195 117 77 67 xx xx OB 55 to OB 57 583 435 283 248 xx xx ...

Page 150: ...Information Functions Module Identification 0111 One ident data record only CPU Characteristics 0012 CPU features all features 0112 Features of a group 0F12 Only SSL partial list header information User Memory Area 0F12 Only partial list header information User Memory Area 0113 Data record for specified memory area Work memory ...

Page 151: ...lock types data records for all block types Status Module LEDs 0019 Status of all module LEDs 0F19 Only partial list header information Component Identification 001C Identification of all components 011C Identification of one component 021C Identification of all components of an H system CPU 031C Identification of a component of all redundant CPUs of an H system 0F1C Only SSL partial list header i...

Page 152: ...on and the corresponding OB 0225 Assignment between an OB and the corresponding process image partitions 0F25 Only SSL partial list header information Communication Status Data 0132 Status data for a communication unit 0232 Status data for a communication unit H CPU Group Information 0071 Information on the current status of the H system 0F71 Only partial list header information Status of the Modu...

Page 153: ... 0191 Status information of all modules racks with incorrect type IDs 0291 Module status information of all faulty modules 0391 Module status information of all unavailable modules 0591 Module status information of all submodules of the host module 0991 Status information of all submodules in the host module in the rack 0C91 Status information of a module in the central rack or connected to an int...

Page 154: ...s of the stations of a DP master system which is connected via an external DP interface module 0392 Status of the back up battery of a CPU rack if at least one battery fails 0492 Status of the entire back up batteries of all racks of the a CPU 0592 Actual status of the racks in the central configuration stations of DP master system which is connected via an external DP interface module 0692 OK sta...

Page 155: ...pplied 00A0 All current diagnostic entries available in current operating mode 01A0 Last x entries X is listed in index 0FA0 Only partial list header information Module Diagnostic Data 00B1 First four diagnostic bytes of a module DS0 00B2 All diagnostic data of a module v 220 bytes DS1 no DP module 00B3 All diagnostic data of a module v 220 bytes DS1 00B4 Diagnostic data of a DP slave with logical...

Page 156: ...abetical Index of Instructions Instruction Page 29 MCR 97 70 AR1 71 AR2 71 D 63 I 61 R 65 D 63 I 61 R 65 D 63 I 62 R 65 D 64 I 62 R 65 40 D 73 I 72 R 74 Instruction Page D 73 I 72 R 74 D 73 I 72 R 74 D 73 I 72 D 73 I 72 R 74 D 73 I 72 R 74 ABS 66 ACOS 69 ASIN 69 ATAN 69 CAD 79 CAR 58 ...

Page 157: ...BEC 89 BEU 89 BLD 81 BTD 82 BTI 82 CALL 86 CC 87 CLR 41 COS 69 DEC 80 DTB 83 DTR 82 ENT 79 EXP 68 FN 38 FP 38 FR 44 46 INC 80 INVD 85 INVI 85 Instruction Page ITB 83 ITD 82 JBI 92 JBIN 92 JCN 91 JC 91 JCB 92 JNB 92 JL 96 JM 94 JMZ 95 JN 94 JO 93 JP 94 JPZ 95 JOS 93 JU 91 L 47 48 49 50 51 52 53 59 60 LAR1 57 LAR2 57 LC 53 ...

Page 158: ...RD 98 MOD 64 NEGD 85 NEGI 85 NEGR 66 NOP 81 NOT 41 O 26 30 32 35 36 37 O 28 OD 34 ON 26 32 35 36 37 ON 28 OPN 88 OW 33 POP 79 PUSH 79 R 39 44 45 RLD 77 RLDA 78 Instruction Page RND 84 RND 84 RND 84 RRD 77 RRDA 78 SAVE 41 SF 43 SE 42 SET 41 SI 42 SIN 69 SLD 75 SLW 75 SQR 67 SQRT 67 SRD 76 SRW 75 S 39 45 SS 43 SSD 76 SSI 76 T 54 55 56 59 ...

Page 159: ...57 S7 400 Instruction List A5E00267845 01 Instruction Page TAK 79 TAN 69 TAR1 58 TAR2 58 TRUNC 84 U 25 31 35 36 37 U 28 UC 87 UN 25 31 35 36 37 Instruction Page UN 28 AW 33 X 27 32 35 36 37 X 28 XN 27 32 35 36 37 XN 28 XOD 34 XOW 33 AD 34 ...

Page 160: ...Alphabetical Index of Instructions 158 S7 400 Instruction List A5E00267845 01 ...

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