Transfer Instructions
56
S7-400 Instruction List
A5E00267845-01
Transfer Instructions, continued
If the used address is divisible by 4without a remainder, the execution times for instructions specified on this page is doubled.
Instruc-
Length
Execution Time in
s
Instruc-
tion
Address
Description
Length
in
Execution Time in
s
tion
Address
ID
Description
in
Words
CPU 412
CPU 414
CPU 416
CPU 417
T
ED
a
AD
a
PAD
a
Transfer contents of
ACCU1 to ...
Input double word
Output double word
periph. output double word
2)
1
1)
/2
1
1)
/2
2
0.1/0.125
0.1/0.125
0.125
0.06/0.075
0.06/0.075
0.075
0.04/0.05
0.04/0.05
0.05
0.03/0.042
0.03/0.042
0.042
MD
a
LD
a
Bit memory double word
Local data double word
1
3)
/2
2
0.1/0.125
0.125
0.06/0.075
0.075
0.04/0.05
0.05
0.03/0.042
0.042
DBD
a
DID
a
Data double word
Instance data double word
2
2
0.11
0.11
0.075
0.075
0.05
0.05
0.042
0.042
T
i [d]
i [AR1,m]
i [AR2,m]
D[AR1,m]
D[AR2,m]
Parameter
Memory-indirect, area internal
Register-ind., area internal (AR1)
Register-ind., area internal (AR2)
Area-crossing (AR1)
Area-crossing (AR2)
Via parameter
2
2
2
2
2
2
0.1+
0.125+
0.125+
0.125+
0.125+
0.125+
0.06+
0.075+
0.075+
0.075+
0.075+
0.075+
0.04+
0.05+
0.05+
0.05+
0.05+
0.05+
0.03+
0.042+
0.042+
0.042+
0.042+
0.042+
+
Plus time required for loading the address of the instruction (see page 20)
1)
With direct instruction addressing; Address area 0 to 127
2)
The following peripheral acknowledgement time must be observed with CPU 414-4H and CPU 417-4H: solo xx
s, redundant xx
s
3)
With direct instruction addressing; Address area 0 to 255