Siemens CPU 412, Instruction Manual

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Edge-Triggered Instructions
38
S7-400 Instruction List
A5E00267845-01
Edge-Triggered Instructions
The current RLO is compared with the status of the instruction or “edge bit memory”. FP detects a change from “0” to “1”; FN detects a
change from “1” to “0”.
Instruc-
Length
in
Execution Time in s
Instruc-
tion
Address ID Description
Length
in
Words
Execution Time in s
Instruc-
tion
Address ID Description
in
Words
CPU 412 CPU 414 CPU 416 CPU 417
FP/FN I/Q a.b
M a.b
L a.b*
)
DBX a.b
DIX a.b
c [d]
The positive/negative edge is
indicated by RLO = 1. The bit
addressed in the instruction is
the auxiliary edge bit memory. 2
2
2
2
2
2 0.2
0.2
0.2
0.3
0.3
0.2+/0.3+
0.12
0.12
0.12
0.18
0.18
0.12+/0.18+
0.08
0.08
0.08
0.12
0.12
0.08+/0.12+
0.06
0.06
0.06
0.12
0.12
0.06+/0.12+ c [d]
c [AR1,m] **
c [AR2,m] **
[AR1,m]**
[AR2,m]**
Parameter** 2
2
2
2
2
2 0.2+/0.3+
0.2+/0.3+
0.2+/0.3+
0.2+/0.3+
0.2+/0.3+
0.2+/0.3+ 0.12+/0.18+
0.12+/0.18+
0.12+/0.18+
0.12+/0.18+
0.12+/0.18+
0.12+/0.18+ 0.08+/0.12+
0.08+/0.12+
0.08+/0.12+
0.08+/0.12+
0.08+/0.12+
0.08+/0.12+ 0.06+/0.12+
0.06+/0.12+
0.06+/0.12+
0.06+/0.12+
0.06+/0.12+
0.06+/0.12+
Status word for: FP, FN BR CC1 CC0 OV OS OR STA RLO /FC
Instruction evaluates: – – – – – – – Yes –
Instruction affects: – – – – – 0 Yes Yes 1
+ Plus time required for loading the address of the instruction (see page 20)
*)
Unnecessary if the bit being monitored is in the process image (local data of a block are only valid while the block is running).
**)
I, Q, M, L /DB, DI