Siemens CPU 412, Instruction Manual

Page: 50 / 160

Load Instructions
48
S7-400 Instruction List
A5E00267845-01
Load Instructions, continued
If there is a remainder of 3 following an integral division of the used addresses by 4, the execution times for instructions specified on this
page are doubled.
In- Length
Execution Time in s
In-
struc-
Address
Description
Length
in
Execution Time in s
struc-
tion
Address
ID
Description
in
Words
CPU 412 CPU 414 CPU 416 CPU 417
L
IW a
QW
PIW
a
Load ...
Input word
Output word
Peripheral input word
2)
1
1)
/2
1
1)
/2
1
1)
/2
0.1/0.125
0.1/0.125
0.1/0.125 0.06/0.075
0.06/0.075
0.06/0.075 0.04/0.05
0.04/0.05
0.04/0.05 0.03/0.042
0.03/0.042
0.03/0.042
MW a
LW a
Bit memory word
Local data word 1
3)
/2
2
0.1/0.125
0.125
0.06/0.075
0.075
0.04/0.05
0.05
0.03/0.042
0.042
DBW a
DIW a
Data word
Instance data word
... into ACCU1-L 2
2 0.2
0.2 0.12
0.12 0.08
0.08 0.09
0.09
h [d]
h [AR1,m]
h [AR2,m]
W[AR1,m]
W[AR2,m]
Parameter Memory-indirect, area-internal
4)
Register-indirect, area-internal (AR1)
4)
Register-indirect, area-internal (AR2)
4)
Area-crossing (AR1)
4)
Area-crossing (AR2)
4)
Via parameter
4)
2
2
2
2
2
2 0.1+/0.2+
0.125+/0.2+
0.125+/0.2+
0.125+/0.2+
0.125+/0.2+
0.125+/0.2+
0.06+/0.12+
0.075+/0.12+
0.075+/0.12+
0.075+/0.12+
0.075+/0.12+
0.075+/0.12+
0.04+/0.08+
0.05+/0.08+
0.05+/0.08+
0.05+/0.08+
0.05+/0.08+
0.05+/0.08+ 0.03+/0.09+
0.042+/0.09+
0.042+/0.09+
0.042+/0.09+
0.042+/0.09+
0.042+/0.09+
+ Plus time required for loading the address of the instruction (see page 20)
1)
With indirect instruction addressing; Address area 0 to 127
2)
The following peripheral acknowledgement time must be observed with CPU 414-4H and CPU 417-4H: solo xx s, redundant xx s
3)
With direct instruction addressing; Address area 0 to 255
4)
I, Q, P, M, L / DB, DI