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Application Examples

SIM 1-2
C79000-G8976-C215-01

4.5 Layout

Proposal

To ensure optimum functionality of the SIM 1-2, certain layout rules should be
adhered to.

●

Connection from pin CRT to base of T1 as short as possible

●

Connection from SENSEP over RSENSEP to capacitor CVE and connection

from SENSEM over RSENSEM to capacitor CVE as short as possible and
symmetrical

●

When using a transformer as DC/DC converter, this should be wired as short

as possible to the switches S1 and S2 and the power supply VE.

Summary of Contents for ASIC SIM 1-2

Page 1: ...unction Manual Preface Area of Application and Characteristics 1 Functional Description of the SIM 1 2 2 Technical Specifications 3 Application Examples 4 Putting into Operation 5 Appendix A Release 02 2007 C79000 G8976 C215 01 ...

Page 2: ...ons are not taken Caution without a warning triangle indicates that damage to property can result if proper precautions are not taken Notice indicates that an undesirable result or status can result if the relevant notice is ignored Note highlights important information on the product using the product or part of the documentation that is of particular importance and that will be of benefit to the...

Page 3: ...duct can only function correctly and safely if it is transported stored set up and installed correctly and operated and maintained as recommended Before you use the supplied sample programs or programs you have written yourself make certain that no injury to persons nor damage to equipment can result in your plant or process EU Directive Do not start up until you have established that the machine ...

Page 4: ...or to Commissioning Prior to commissioning note the following warning Caution Prior to startup read the relevant documentation For ordering data of the documentation please refer to catalogs or contact your local Siemens representative ...

Page 5: ...r the bus can be implemented with little effort This manual serves both as a function manual and as a data sheet for the developer of the electronics Aims With the aid of this manual you will be able to develop a fieldbus medium attachment unit MAU for 31 25 Kbps for your application with little effort using the SIM 1 2 We assume that you are familiar with the relevant standards and specifications...

Page 6: ...Preface SIM 1 2 6 C79000 G8976 C215 01 ...

Page 7: ...al Power Supply VCCD VCCA VM 21 2 3 10 Oscillator XT0 XT1 21 2 3 11 Digital Interface TXE TXS RXA RXS 22 2 3 12 Test and Manufacturing Pins TD T0 T1 T2 TA 22 2 3 13 Mode Setting GIM and VCM 22 2 3 14 Voltage Monitoring 23 2 4 Power Supply of the Application 24 2 4 1 Power Supply VREG 24 2 4 2 Power Supply VE 25 2 4 3 DC DC Converters S1 and S2 26 2 4 4 Dimensioning the Backup Capacitor 27 2 5 Inte...

Page 8: ... Assignment 52 4 4 Circuit Examples 53 4 4 1 Block Diagram of the SIM 1 2 and SPC 4 2 with Galvanic Isolation 53 4 4 2 Diagram of the SIM 1 2 and SPC 4 2 without Galvanic Isolation 54 4 4 3 External Components recommended values 55 4 4 4 Notes on the Transistor 56 4 5 Layout Proposal 57 5 Putting into Operation 59 5 1 Putting into Operation for the First Time 59 5 2 Test Points 60 6 Appendix 61 6 ...

Page 9: ...PC 4 2 devices with a fieldbus attachment can be implemented with little effort The SIM 1 2 supports all send and receive functions including jabber control and the high impedance decoupling of auxiliary energy from the bus cable It provides a selectable stabilized power supply and also allows the setup of an galvanically isolating power supply with a few passive components As an alternative to th...

Page 10: ...es The following diagram illustrates examples of SIM 1 2 applications Bus Speisegerät Power VBUS VBUS Feldbus SIM 1 2 VBUS VBUS Slave Controller Application Controller Aktor SIM 1 2 VBUS VBUS Slave Controller Application Controller Sensor SIM 1 2 VBUS VBUS SPC 4 Application Controller Sensor Power ...

Page 11: ... already include a Manchester encoder decoder in compliance with IEC 61158 2 Jabber inhibit jabber control prevents a node from transmitting indefinitely on the bus Sender with current modulator for bias currents Asymmetric modulation from 2 mA to 10 mA Symmetric modulation from 10 to 50 mA Power optimized electrical isolation The SIM 1 2 supports simple and power minimized galvanic isolation betw...

Page 12: ... to SMD housing MLPQ 40 Ambient temperature range 40 to 85 C Low current consumption for own supply Bus voltage 9 V to 32 V functional range Stabilized output voltage for the user Can be set in the range from 2 V to 5 V tolerance 3 Up to 50 mA total available On chip voltage reference On chip voltage monitoring On chip RESET and PDWN for safe power up and power down management of connected logic c...

Page 13: ...ce Logik TXE TXS RXA2 RXS Bandpass 2 Ordnung Tiefpass 2 Ordnung Shunt Regulator 6 3V VCC Regulator 5V Clock Generator Power Management Current control VREG Regulator VCCD VCCA VREG DC DC DC DC Control RSENSEP T1 US Receiver Filter und Komparator S1 RESETXN PDWNXN S2 RxF REx1 CRXIN CVE CVCC CVREG CTR TXE2 TXS2 RXA RXS2 TXE1 TXS1 RXA1 RXS1 VBUS RSENSEM SENSEP RVREG Referenz control RVCCVE RIREF RISO...

Page 14: ...nternal reference current with possible external adjustment 5 RISOLL I O A Set reference for bus current control 2 mA to 50 mA corresponds to 0 1 MΩ to 2 5 MΩ 6 RVCCVE I O A Generation of an internal reference voltage and at the same time measuring point for an external adjustment to RIREF target U RVCCVE 1 V 7 RVREG I O A Set reference for VREG 2 V to 5 V corresponds to 1 0 MΩ to 2 5 MΩ 8 GND P A...

Page 15: ...Galvanic isolation mode enabling of power saving interface 28 GND P D Ground 29 PROG P D Must be connected to VCCD 30 VCCD P D Regulated supply voltage 5 V for digital circuit 31 XT1 I O D Quartz or resonator connector with external clock supply XT1 used as input 32 XT0 I O D Quartz or resonator connector with external clock supply XT0 is connected to GND 33 VCCA P A Regulated supply voltage 5 V f...

Page 16: ...in Arrangement Pin layout in the 40 pin housing 40LD MLPQ 6x6 VJJD 2 T0 TD PDWNXN RESETXN TxS TxE RxA RxS GND VREG S2 GND S1 T1 T2 VCM GIM GND PROG VCCD VESRD VE GND RVREG RVCCVE RISOLL RIREF SENSEM SENSEP CTR XT1 XT0 VCCA GND TA VM RDCDC RXIN GND VBUS 1 10 11 20 21 30 31 40 41 ...

Page 17: ...to the negative side of the bus system is over GND As an alternative to a diode as polarity reversal protection a rectifier bridge can be used as polarity reversal protection and feedback protection 2 3 2 Control Loop CTR This output controls the base of the external PNP transistor T1 that supplies the local consumer connected to VE and switches to output signal to the bus by modulating the curren...

Page 18: ...an the current transferred to the application over VREG and VE including DC DC RRISOLL MΩ 0 05 IBUS mA Conditions for RRISOLL 100 KΩ RRISOLL 2 5 MΩ the capacitor CVE must be dimensioned in the permitted range according to the pulse load by the application or the DC DC converter Caution 1 To achieve the minimum bus current tolerance of 3 resistors with a tolerance of 0 1 must be used As an alternat...

Page 19: ... mA CEMC 190 pF 40 mA CEMC 0 pF As of a current of 40 mA CEMC remains 0 pF At IBUS currents 40 mA the required impedance at 39 kHz for bus voltages UBUS 12 V is not achieved System Stability We recommend the transistor PZT3906 If you set the IBUS current to 30 mA you should use an additional L_SENSE inductor of 1 µH This avoids self excitation and increases system stability The L_SENSE inductor is...

Page 20: ...SOLL Connect the contacts to the specified reference resistors Contact Reference resistor Meaning RIREF RRIREF All internal references are derived from the current flowing through RRIREF RVCCVE RRVCCVE RRVCCVE forms the reference for VCC and VE The RVCCVE pin must be backed up to GND by capacitor CRVCCVE RVREG RRVREG RRVREG forms the reference for VREG The RVREG pin must be backed up to GND by cap...

Page 21: ...cation Voltage VREG With VREG there is an operating voltage regulated by RRVREG in the range from 2 V to 5 V for local loads This is also the power supply for the outputs and inputs of the digital interface TXE TXS RXA RXS RESETXN PDWNXN 2 3 9 Internal Power Supply VCCD VCCA VM The two pins VCCD and VCCA must be connected directly with each other and backed up to GND over the capacitor CVCC No pow...

Page 22: ...nically isolated over optocouplers for the external application electronics Interfacing using the power saving galvanic signal isolation over two optocouplers TXS and RXS 2 3 12 Test and Manufacturing Pins TD T0 T1 T2 TA For the SIM 1 2 to function perfectly the test and manufacturing pins TD T0 T1 T2 and TA must be connected to GND 2 3 13 Mode Setting GIM and VCM Galvanic Isolation Mode GIM This ...

Page 23: ...n the SIM 1 2 signals the end of the startup phase with a change from low to high This means that all required power supplies have reached their desired value If the VREG voltage sinks below 90 of the desired value VREGSOLL a change from high to low at the RESETXN pin signals the reset status of the chip PDWNXN pin At the PDWNXN pin the SIM 1 2 signals an interruption of the bus supply with a shor...

Page 24: ... 4 1 Power Supply VREG The VREG voltage that can be set between 2 V and 5 V regulated by RRVREG is available as a non floating power supply for the external application electronics The VREG power supply can be subjected to a maximum load of 50 mA RRVREG MΩ 0 5 VREG V Conditions for RVREG 1 MΩ RVREG 2 5 MΩ Notice You achieve the minimum VREG tolerance of 3 if you use a resistor with a tolerance of ...

Page 25: ...ronics It is however important to make sure that the VE never falls below 80 as a result of sudden load changes If the VE voltage sinks below 90 of VESOLL a prewarning PDWNXN low active is output PDWNXN changes to logic 0 for 10 µs Communication over TxE TxS RxA and RxS is not affected by this If the VE voltage falls below 80 of VESOLL the DC DC converter and the VREG regulator are turned off They...

Page 26: ...the leakage inductance of the transformer can induce brief voltage peaks when switching the transistor bridge circuit breaker that are far higher than twice the value of VE and therefore destroy the circuit breaker To prevent this the voltage is limited internally to approximately 20 V The ability of this voltage limitation to absorb is however limited to the energy stored in a leakage inductance ...

Page 27: ...on and the backup capacitors CVE and CDCDC must be matched up Secondary capacitor CDCDC The dimensions of the secondary capacitor of transformer CDCDC must not be too large depending on the constant current CDCDC IBUS 0 5 µF mA Capacitor CVE The following applies to capacitor CVE CVE 2 Ü CDCDC where Ü VDCDC VE Capacitor CVREG The following applies for capacitor CVREG CVREG 47 µF ...

Page 28: ...nt regulator derives a stabilized voltage VE from the constant current The part of the total current not required by external loads is diverted to GND The load current can be taken in any proportions from the power supplies VREG and the DC DC converter external transformer necessary 2 5 3 Signal Filter The combined input high pass band pass and low pass filter suppresses disturbances outside of th...

Page 29: ...ng node for blocking the transmission medium jabber inhibit The SIM 1 2 meets the standard IEC 61158 2 It specifies that transmission of a message to the medium will be interrupted if the message duration exceeds a time of 120 to 240 ms At the same time the transmission of the RxS1 data and the RxA1 signal to the node must be inhibited After a time of 3 s 50 the inhibit is canceled and monitoring ...

Page 30: ... L on the interface are passed on without any processing and switched through to the user electronics The output level of RxA and RxS is adapted over the interface and application voltage VREG Conventional isolation with optocouplers To achieve galvanic isolation of the lines for data and associated signals various isolating components and circuits can be used One common method is to provide an op...

Page 31: ...SIM 1 2 C79000 G8976 C215 01 31 Technical Specifications 3 This section contains the technical specifications of the SIM 1 2 ...

Page 32: ...ltages relate to GND A current flowing out of a pin is preceded by a negative sign Values for bus interfacing Name pin Parameters Min Max Unit Remark VBUS Supply voltage 0 3 35 0 V SENSEP SENSEM CTR RXIN Voltage at the inputs and outputs 0 3 VBUS 0 3 V RXIN over REX1 and CTR I CTR Control current at base of T1 5 5 mA Values for supply VE Name pin Parameters Min Max Unit Remark VE Supply voltage 0 ...

Page 33: ...es for supply VREG Name pin Parameters Min Max Unit Remark VREG Supply voltage 0 3 7 0 V I VREG Load current 55 300 mA The maximum is the peak value if a short circuit occurs TxE TxS RxA RxS PDWMXN RESETXN Voltage at the inputs and outputs 0 3 VREG 0 3 V I RxA I RxS Load current 2 16 mA IOH IOL I PDWMXN I RESETXN Load current 1 5 mA IOH IOL Values for DC DC activation Name pin Parameters Min Max U...

Page 34: ... operating temperature 135 preliminary C Operating junction Temperature Rth j a Heat transfer resistance junction environment 26 K W Thermal resistance from junction to ambient in free air Housing Solder profile Pb free JEDEC J STD 020C Housing Solder temperature 260 C JEDEC J STD 020C Housing Moisture sensitivity level l MSL 3 JEDEC J STD 020C All pins Lead finish Sn Pb free All pins ESD resistan...

Page 35: ...operating conditions and characteristic data of the SIM 1 2 and are structured according to the corresponding power supply The information covers the spread of values that must be kept to at a bus voltage VBUS of 9 V to 32 V and an ambient temperature of 40 C to 85 C All voltages relate to GND A current flowing out of a pin is preceded by a negative sign ...

Page 36: ... 4 0 55 0 75 mA Bypass current IVBUSBYPASS Own current requirements startup bypass 40 µA Own power requirements VBUS SENSEP SENSEM Voltage at SENSEP and SENSEM 7 5 V I SENSEP Current SENSEP pin 0 75 mA Bypass current I SENSEM Current SENSEM pin 0 6 mA Compensation current RSENSEP RSENSEM Actual current value detection 10 Ω 0 1 tolerance and TK 15 ppm K to achieve 3 tolerance of the circuit CTR Con...

Page 37: ...016R TAJC107K010R RRIREF Reference current generation 1 5 MΩ 2 RRVCCVE Reference voltage generation for VCC and VE 1 0 MΩ 2 RRVREG Reference voltage generation for minimum value VREG 2 V 1 0 MΩ 2 RRVREG Reference voltage generation for maximum value VREG 5 V 2 5 MΩ 2 RRISOLL Bus current setting for minimum value IBUS 2 mA 100 kΩ 2 RRISOLL Bus current setting for maximum value IBUS 50 mA 2 5 MΩ 2 C...

Page 38: ...5 plus the vendor specific initial tolerance for the typical value XT0 XT1 Voltage at XT0 and XT1 0 3 VCCA 0 3 V CXT0 CXT1 Load capacitance 10 47 pF VCM GIM Input signal high 4 0 V VCM GIM Input signal low 1 0 V VCM GIM Input signal hysteresis 0 5 V VCM GIM Input current 10 µA VIN GND to VCCD Values for supply VREG Name pin Parameters Min Typ Max Unit Remark VREG Desired voltage at VREG 2 V 1 94 2...

Page 39: ...e Name pin Parameters Min Typ Max Unit Remark RESETXN PDWNXN Output signal VOH 0 8 VREG V IOH 1 mA RESETXN PDWNXN Output signal VOL 0 4 V IOL 5 mA RxA RxS Output signal VOH VREG 0 1 V IOH 0 1 mA RxA RxS Output signal VOH VREG 0 5 V IOH 0 8 mA RxA RxS Output signal VOL 0 1 V IOL 0 1 mA RxA RxS Output signal VOL 0 4 V If IOL 10 mA and VREG 3 V to 5 V If IOL 4 mA and VREG 2 V to 3 V TxE TxS Input sig...

Page 40: ...Technical Specifications SIM 1 2 40 C79000 G8976 C215 01 Values for environmental influences Name pin Parameters Min Typ Max Unit Remark TOP Ambient temperature 40 85 C In operation ...

Page 41: ...Technical Specifications SIM 1 2 C79000 G8976 C215 01 41 3 3 Housing MLPQ 40 Drawing of the Housing ...

Page 42: ...215 01 Housing Dimensions The following table lists the dimensions of the housing in millimeters Meaning Min Typical Max A 0 8 0 9 1 0 A1 0 0 02 0 05 A3 0 2 D 6 0 D2 4 0 4 15 4 25 I 6 0 E2 4 0 4 15 4 25 e 0 5 L 0 3 0 4 0 5 L1 0 03 0 15 b 0 18 0 25 0 30 ...

Page 43: ...e Sensitivity Level 3 The component must then by dried at 125 C for 24 hours and processed within 48 hours This drying may only be performed once due to the solderability of the component according to JEDEC J STD 020C Moisture Sensitivity Level 3 The SIM 1 2 is approved for infrared reflow with the lead free reflow profile according to JEDEC JSTD 020C The lead free infrared reflow process must not...

Page 44: ...Technical Specifications SIM 1 2 44 C79000 G8976 C215 01 ...

Page 45: ...utput voltage VREG as reference voltage Conventional isolation with optocouplers To achieve galvanic isolation of the lines for data and associated signals various isolating components and circuits can be used The conventional method is a separate optocoupler each for the signals TxS TxE RxS and RxA Figure b Power saving isolation With the power saving galvanic isolation only two optocouplers are ...

Page 46: ...Application Examples SIM 1 2 46 C79000 G8976 C215 01 ...

Page 47: ...odulator converts the serial signal to be transferred into a duration modulated pulse train in which the rising edge of the send signal is assigned a long pulse and the falling edge a short pulse A long and a short pulse are also generated with the edges of the static associated signal and added to the pulse train of the data signal The total signal generated in this way is used to drive the LED o...

Page 48: ...old on the comparator leads to different delays of the edges causing unacceptable signal distortions It is possible to minimize the distortion if the when the switching times of the comparator are close to the beginning of the signal changes This however requires different switching thresholds dependent on the edge or signal directions A suitable adaptation of the switching threshold can be implem...

Page 49: ...fore corresponds to the serial data signal The output signal of a further flip flop FF 2 is ORed with signal If two short pulses occur one after the other both flip flops are reset The OR operation results in an L which is detected as the end of the static signal A further triggerable delay element t4 40 s t4 100 µ s resets both evaluation flip flops with the signal in transmission pauses to suppr...

Page 50: ...Application Examples SIM 1 2 50 C79000 G8976 C215 01 Signal Evaluation in the Demodulator ...

Page 51: ...ge of the comparator to the middle of the SPC 4 2 supply voltage VCC The difference between the values of R2 and R4 results in an offset in the quiescent state R6 brings about a reduction in amplitude and C2 a delay of the reference voltage in the active state The capacitor C1 decouples the supply voltage of the optocoupler from the communication controller supply voltage VCC Example of Demodulato...

Page 52: ...ssignment Description On the SIM 1 2 the signals are assigned in compliance with the IEC 61158 2 standard The figure below describes the assignment of the logical state of TxS to the signal adjustment VBus VBus or the assignment of VBus VBus to RxS Signal Assignment ...

Page 53: ...Application Examples SIM 1 2 C79000 G8976 C215 01 53 4 4 Circuit Examples 4 4 1 Block Diagram of the SIM 1 2 and SPC 4 2 with Galvanic Isolation ...

Page 54: ...Application Examples SIM 1 2 54 C79000 G8976 C215 01 4 4 2 Diagram of the SIM 1 2 and SPC 4 2 without Galvanic Isolation ...

Page 55: ... 15 ppm K REX1 Input high pass 10 kΩ 1 100 ppm K RRDCDC DC DC startup current limitation 56 kΩ 0 1 15 ppm K CVE Backup capacitance Tantalum TAJA475K016R TAJC107K010R 4 7 to 100 µF 10 10 V CVREG Backup capacitance Tantalum TAJA475K016R TAJA226K016R 4 7 to 22 µF 10 10 V CVCC Backup capacitance Tantalum TAJA105K016R TAJA335K016R 1 0 to 3 3 µF 10 10 V CVM Backup capacitance Ceramic 100 nF 5 CRXIN Inpu...

Page 56: ...ing self excitation an inductor 3 3 µH must be included in series in addition to the RSENSEP measuring resistor see section 2 3 3 Current Sensing by SENSEP and SENSEM Please not the following restrictions regarding EMC capacitance for the transistor PZT2907A 10 mA IBUS 50 mA CEMC 500 pF With the transistor PZT2907A and an EMC capacitance CEMC 500 pF the required impedance is achieved at 39 kHz for...

Page 57: ...adhered to Connection from pin CRT to base of T1 as short as possible Connection from SENSEP over RSENSEP to capacitor CVE and connection from SENSEM over RSENSEM to capacitor CVE as short as possible and symmetrical When using a transformer as DC DC converter this should be wired as short as possible to the switches S1 and S2 and the power supply VE ...

Page 58: ...Application Examples SIM 1 2 58 C79000 G8976 C215 01 ...

Page 59: ...first time check the correct wiring and components according to the block diagrams In particular check the reference resistances RRIREF RRISOLL RRVCCVE and RRVREG and the connection VE VESRD and the connection VCCA VCCD Caution An interruption at the reference resistances RRIREF and RRISOLL during operation can lead to damage destruction of the SIM 1 2 ...

Page 60: ... Description VE Voltage at pin VE VESRD 6 3 V VCC Voltage at pin VCCA VCCD 5 0 V VREG Voltage at VREG pin according to RRVREG tolerance IBUS Total current consumption according to RRISOLL tolerance Check whether or not the voltages and the current are within the tolerance range resulting from the tolerance of the selected resistors from the tolerance calculation in section 2 3 7 ...

Page 61: ...ldbus for use in industrial control systems Part 2 Physical layer specification and service definition 2 PROFIBUS Test Guidelines for Field Devices according to PROFIBUS PA Profile for Process Control Devices Version 3 0 Version 3 1 April 2000 Order number 2 061 3 FOUNDATION Specification 31 25 Kbps Physical Layer Conformance Test ...

Page 62: ...658 590 Technical Information in Germany and Europe Siemens AG A D SE RD73 Postfach 2355 90713 Fürth Germany Tel 49 911 750 2080 Fax 49 911 750 2100 E mail comdec siemens com Technical Information Outside Europe PROFIBUS Interface Center One Internet Plaza PO Box 4991 Johnson City TN 37602 4991 Fax 01 423 262 2103 BBS 01 423 262 2576 E mail profibus center sea siemens com ...

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