Application Examples
SIM 1-2
C79000-G8976-C215-01
49
Description of the Signal Evaluation
The leading edge on an incoming pulse
➁
triggers a time stage with a run time of
t3. The following time condition applies: t1
<
t3
<
t2.
On expiry of t3, a scan for pulse length t1 or t2 is performed. Depending on the
detected pulse length t1 or t2, the flip-flop FF 1 is set to L or H. The output of the
flip-flop therefore corresponds to the serial data signal
➃
. The output signal
➄
of a
further flip-flop FF 2 is ORed with signal
➃
. If two short pulses occur one after the
other, both flip-flops are reset. The OR operation results in an L, which is detected
as the end of the static signal
➅
. A further triggerable delay element t4 (40 *s * t4 *
100
µ
*s) resets both evaluation flip-flops with the signal
➆
in transmission pauses
to suppress undefined signals being set as a result of noise.
Pulses < 0.5 *s at the comparator output will be suppressed reliably, pulses * 1
µ
s
will be reliably detected.
Principle of Demodulator Signal Evaluation
Summary of Contents for ASIC SIM 1-2
Page 6: ...Preface SIM 1 2 6 C79000 G8976 C215 01 ...
Page 44: ...Technical Specifications SIM 1 2 44 C79000 G8976 C215 01 ...
Page 46: ...Application Examples SIM 1 2 46 C79000 G8976 C215 01 ...
Page 50: ...Application Examples SIM 1 2 50 C79000 G8976 C215 01 Signal Evaluation in the Demodulator ...
Page 58: ...Application Examples SIM 1 2 58 C79000 G8976 C215 01 ...
