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SDRAM RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate
its charge before DRAM refresh, the refresh may be-incompleted, and
the DRAM may fail to retain data. Fast gives faster performance; and
Slow gives more stable performance. This field is applied only
when synchronous DRAM is installed in the system.
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The Choice: 2 or 3.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-
FFFFFh, resulting in better system performance. However, if any pro-
gram is written to this memory area, a system error may result.
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The choice: Enabled or Disabled.
Video BIOS Cacheable
Selecting Enabled allows caching of the video BIOS , resulting in better
system performance. However, if any program is written to this memory
area, a system error may result.
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The Choice: Enabled or Disabled.
Memory Hole At 15M-16M
You can reserve this area of system memory for ISA adapter ROM.
When this area is reserved, it cannot be cached. The user information
of peripherals that need to use this area of system memory usually
discusses their memory requirements.
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The Choice: Enabled or Disabled.
CPU Latency Timer
This item Enable/Disable the deferrable CPU cycle being deferred when
other device access memory.
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The Choice: Enabled or Disabled.
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support
delayed transactions cycles. Select Enabled to support compliance with
PCI specification version 2.1.
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The Choice: Enabled or Disabled.
Local Memory Frequency
Select the memory frequency.
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The Choice: 100MHz or 133MHz.
