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DRAM Data Integrity Mode
Select Parity or ECC (Error-Correcting Code), according to the type of installed DRAM.
The Choices: Non-ECC, ECC.
System BIOS Cacheable
Select Enabled allows caching of the system BIOS ROM at F000h-FFFFFh, resulting in
better system performance. However, if any program writes to this memory area, a
system error may result.
The Choice: Enabled, Disabled.
Video BIOS Cacheable
Select Enabled allows caching of the video BIOS ROM at C000h-F7FFFh, resulting in
better video performance. However, if any program writes to this memory area, a system
error may result.
The Choice: Enabled, Disabled.
Video RAM Cacheable
This is a new cache technology for the video memory of the processor. It can greatly
improve the display speed by caching the display data. You must leave this on the default
setting of
Disabled
if your display card cannot support this feature or else your system
may not boot.
8 Bit I/O Recovery Time
The recovery time is the length of time, measured in CPU clocks, which the system will
delay after the completion of an input/output request. This delay takes place because the
CPU is operating so much after than the input/output bus that the CPU must be delayed to
allow for the completion of the I/O.
This item allows you to determine the recovery time allowed for 8 bit I/O. Choices are
from NA, 1 to 8 CPU clocks.
16-Bit I/O Recovery Time
This item allows you to determine the recovery time allowed for 16 bit I/O. Choices are
from NA, 1 to 4 CPU clocks.
Memory Hole At 15M-16M
In order to improve performance, certain space in memory can be reserved for ISA cards.
This memory must be mapped into the memory space below 16 MB.
Passive Release
When enabled, the chipset provides a programmable passive release mechanism to meet
the required ISA master latencies.
Delayed Transaction
Since the 2.1 revision of the PCI specification requires much tighter controls on target
and master latency. PCI cycles to or from ISA typically take longer. When enabled, the
chipset provides a programmable delayed completion mechanism to meet the required
target latencies.
