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SDRAM PH Limit
This item set the number of consecutive page-hit requests to allow
before choosing a non-page-hit request.
The choice: 1 Cycle, 4 Cycle, 32 Cycle, 64 Cycle,
SDRAM Idle Limit
This item set the number of idle cycles to wait before precharging an
idle bank.
The choice: 0 Cycle, 8 Cycle, 12 Cycle, 16 Cycle, 24 Cycle,
32 Cycle, 48 Cycle.
SDRAM Trc Timing Value
This item set the minimum time from activate to activate of the same
bank.
The choice: 3 Cycle, 4 Cycle, 5 Cycle, 6 Cycle, 7 Cycle, 8 Cycle.
SDRAM Trp Timing Value
This item set the delay from precharge command to activate
command.
The choice: 2 Cycle, 3 Cycle.
SDRAM Tras Timing Value
This item set the mimimum bank active time.
The choice: 2 Cycle, 3 Cycle, 4 Cycle, 5 Cycle, 6 Cycle, 7 Cycle.
SDRAM CAS Latency
This item set the delay from SCAS to data valid.
The choice: 2 Cycle, 3 Cycle.
SDRAM Trcd Timing Value
This item set the delay from the activation of a bank to the time that a
read or write command is accepted.
The choice: 1 Cycle, 2 Cycle, 3 Cycle, 4 Cycle.
