The copy lamp is switched by the triac. At the rising of CLPWM signal
(V4), the trigger signal CL is sent to the triac to light the lamp. The
lamp will goes off later at the zero cross point of V1 waveform.
The CPU reads the control voltage level (CLV) corresponding to the
change in the copy lamp voltage, and compares it with the reference
level to change the ON period of the output pulse.
The CLV forms the same waveform as the copy lamp voltage
waveform where the Ac input’s full rectified waveform (FW) is dis-
abled for ON periods of the pulse. It is converted into a DC level by
the low pass filter composed of C107 and R168, and is inputted to the
CPU.
The relationship between the CLV and the pulse ON period is as
shown in the figure below:
•
When the pulse ON period is shorter, the CLV becomes higher,
and vice versa.
•
The pulse ON period rises at he AC zero cross timing and is driven
by the duty.
•
The copy lamp lighting signal generates positive pulses with C133
at falling of the CPU output, and inputs the pulses through the
two-stage transistor to the photo triac.
•
Section A in the figure shows the circuit which prevents against
application of an overvoltage to the copy lamp.
When the pulse on period is abnormally short, the DC level applied
to the IC112 10 pin becomes higher than the reference voltage of
11 pin, driving the 13 pin output to the GND level.
Therefore the lighting signal is not transmitted to R174 and later
section and the lamp is not lighted.
By setting the reference voltage to a level not exceeding the rated
voltage, an abnormal lighting is avoided.
1
When the AC input voltage becomes low (with the copy lamp
control voltage at constant):
The FW peak at point
becomes lower to decrease the CLU
voltage at
.
Then the CPU shortens the output pulse ON period until the CLV
reaches the reference level, increasing the power applied to the
coy lamp.
2
When the Ac input voltage becomes higher (with the copy lamp
control voltage at constant):
The reversed operations of
1
are performed to lengthen the
output pulse ON period, decreasing the current flowing through
the copy lamp.
3
When the copy lamp control voltage is decreased:
The CLV reference level in the CPU is lowered. The output pulse
ON period is lengthen until the CLV reaches the level, decreasing
the power supplied to the copy lamp.
4
When the copy lamp control voltage is increased:
The reversed operations of
3
are performed, to shorten the out-
put pulse ON period, increasing the power applied to the copy
lamp.
0V
0V
0V
0V
+5V
0V
0V
VCL
V5
V4
V3
V2
V1
8 or 10 msec
50Hz
60Hz
CLV
(V)
(msec)
CPU output (CLPWM)
Pulse ON (Changeing)
Pluse ON period
V1
V3
12 – 10
