(2) Display circuit
Control is performed with the data signal and the control signal from
the control circuit.
1
Block diagram
2
Operation
DAta signal (8 bit) sent from the main control PWB is shifted at the
rising timing of the clock and retained at the rising timing of the latch
signal.
The retained data is outputted when STROBE signal becomes HIGH
(5V).
VD
CLK LATCH
S IN
OUT
VD (+5V)
VD (+10V)
LED
DATA
CLK
LATCH
ENABLE
S OUT
BEO
Main
control
circuit
STROBE
VD (+5V)
DC power
circuit
VD (+5V) VD (+10V)
DATA
Sout
CLK
LATCH
ENABLE
GND
32 bit Shift Register
32 bit Latch
Driver ON/OFF Control
Driver
01
032
VD
GND
1
5V
5V
5V
1
2
3
4
Clock
Data signal
Latch signal
Strobe signal
Output LED
51
52
LED light
up at LOW
level (0V)
8
12 – 12
