– 83 –
MD-X60H
IC901 RH-iX2757AFZZ:System Control Micon (3/4)
53
SPEANA-Lch
P10/AN10
Input
–
–
AOUT input of Lch side BA3835S. A/D input
54
SPEANA-Lch
P11/ANI1
Input
–
–
AUTO input of Rch side BA3835S. A/D input
55
JOG-A
P12/ANI2
Input
L
H
JOG input A. Port input. External PUL-UP is required.
56
JOG-B
P13/ANI3
Input
L
H
JOG input B. Port input. External PUL-UP is required.
57
POSISTER
P14/ANI4
Input
–
–
POWER IC posister value detection. A/D input
58
Initial Setting
P14/ANI5
Input
–
–
Setting of destination with A/D value
59
SPAN Slection
P14/ANI6
Input
L/H
–
TUNER span selection. Port input
60
VSM
P14/ANI7
Input
–
–
Input of intensity of electric field in state of RDS ASPM
with A/D value
61
–
AVSS
Input
–
–
A/D converter ground potential. To be connected to VSS
62
FLD CS1
P130/AN00
Output
L
H
FL driver. M35500AFP chip selection output
63
FLD CS2
P131/AN01
Output
L
H
FL driver. M66004FP chip selection output
64
–
AVREF1
Input
–
H
D/A converter reference voltage input.
To be connected to VDD.
65
FLD A/D IN
P70/RXD2
Input
L/H
–
Serial data input from FL driver M35500AFP
SI2
Taking-in of key input with 6 byte A/D value
66
FLD DATA
P71/RXD2
Output
L/H
L
Serial data output to M35500AFP/M66004FP
SO2
Indication data output
67
FLD SCLK
P72/ASCK2
Output
L
H
Serial clock output to M35500AFP/M66004FP
SCK2
68
MD-DATA
P20/RXD1
Input
L/H
–
Serial data input from MD microcomputer
SI1
69
K-DATA
P21/TXD1
Output
L/H
H
Serial data output to MD microcomputer
SO1
70
DSCK
P22/ASCK1
Output
L
H
Serial clock output to MD microcomputer
SCK1
71
RES
P23/PCL
Output
L
H
Reset output to CD DSP element
72
RWC
P24/BUZ
Output
L/H
H
READ/WRITE control output to CD DSP element
73
SQOUT
P25/SI0
Input
L/H
–
Serial input of sub-code data Q from CD DSP
74
COIN
P26/SO0
Output
L/H
H
Serial output of command data to CD DSP
75
CQCK
P27/SCK0
Output
L
H
Serial clock output to CD DSP
76
WRQ
P80/A0
Input
H
L
Sub-code Q output standby input
77
DRF
P81/A1
Input
H
L
RF level detection input. (DETECT RF)
78
SL+
P82/A2
Output
H
L
Slide feed signal
79
SL-
P83/A3
Output
H
L
Slide feed signal output -
80
PU IN
P84/A4
Intput
L
L
Pickup innermost periphery detection SW input.
Innermost periphery: L
81*
HS
P85/A5
Output
H
L
CD x2 speed control output.
x2 speed: H output, Usual speed: L output
82*
C.MUTE
P86/A6
Output
–
L
83
L.MUTE
P87/A7
Output
H
H
AUDIO system line mute output
ON: H output, OFF: L output
84
CCB-CE
P40/AD0
Output
L
H
Chip enable output to AUDIO/PLL/RDS element of CCB
communication
85
CCB-DO
P41/AD1
Input
L/H
–
serial data input from PLL/RDS element of CCB
communication
86
CCB-DI
P42/AD2
Output
L/H
H
serial data output to AUDIO/PLL/RDS element of CCB
communication
87
CCB-CL
P43/AD3
Output
L
H
Serial clock output to AUDIO/PLL/RDS element of CCB
communication
88
S.MUTE
P44/AD4
Output
H
H
AUDIO system mute output
89*
Not Used
P45/AD5
Output
–
L
90*
Not Used
P46/AD6
Output
–
L
91
TUNER MUTE
P47/AD7
Output
H
H
TUNER MUITE control
ON: H output, OFF: L output
92
SD
P50/A8
Input
L
H
SD input in case of TUNER AUTO SCAN
Pin No.
Function
Terminal Name
Input/Output
Port Name
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Active
Level
Setting
in Reset
