Sharp LS013B7DH01, Technical Literature

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SPEC No.
LCP-2110019B
MODEL No.
LS013B7DH01
PAGE
16
6-5-2 Data Update Mode (Multiple Lines)
Updates arbitrary multiple lines data. (M0=”H”
、
M2
＝
”L”)
M0: Mode flag. Set for “H”. Data update mode (Memory internal data update)
When “L”, display mode (maintain memory internal data).
M1: Frame inversion flag.
When “H”, outputs VCOM=”H”, and when “L”, outputs VCOM=”L”.
When EXTMODE=”H”, it can be “H” or “L”.
M2: All clear flag.
Refer to 6-5-4) All Clear Mode to execute clear.
DUMMY DATA: Dummy data. It can be “H” or “L” (“L” is recommended.)
※
For gate line address setting, refer to 6-6) Input Signal and Display.
※
Input data continuously.
※
M1: Frame inversion flag is enabled when EXTMODE=
”
L
”
.
※
When SCS becomes
“
L
”
, M0 and M2 are cleared.
DUMMY DATA(don't care)
DUMMY DATA(don't care)
DUMMY DATA(don't care)
DMY
D143 D144 D2 D1
AG0 AG1 AG2 M0 M2 DMY DMY M1 DMY DMY D2 AG1 D4 AG0 D141 D144 D142 D143 D1 D1 D2 D3 AG7 AG6 AG3 AG7 AG6 AG5 AG4
D143 AG7 AG6 AG5 AG0 AG1 AG2 D144
tsSI thSI
tsSCS
GL1st line GL2nd line
GL(n)th line
Data transfer period
(16ck)
GL(n-1)th line
thSCS
twSCLKH twSCLKL
twSCSL twSCSH
twSCSH
Data transfer period
(8ck(Dummy)+8ck(Address)=16ck)
SCS
SI
SCLK
Data writing period
(144ck)
Mode selection period
(3ck+5ckDMY)
Gate line address period
(8ck)
Data writing period
(144ck)
Data transfer period
(8ck(Dummy)+8ck(Address)=16ck)
Data writing period
(144ck)
※ Data write period
Data is being stored in 1
st
latch block of binary driver on panel.
※
Data transfer period
For example, during GL2nd line data transfer period, GL 2
nd
line address is latched and GL1st
line data is transferred from 1
st
latch to pixel internal memory circuit at the same time.