Sharp LC-40LS340E, Service Manual

Page: 40 / 122

LC-32LE340/343
LC-40LE340/343
24
The Spartan-3E family builds on the success of the earlier Spartan-3 family by increasing the
amount of logic per I/O, significantly reducing the cost per logic cell. New features
improve system performance and reduce the cost of configuration. These Spartan-3E
enhancements, combined with advanced 90 nm process technology, deliver more
functionality and bandwidth per dollar than was previously possible, setting new standards in
the programmable logic industry. Because of their exceptionally low cost, Spartan-3E FPGAs
are ideally suited to a wide range of consumer electronics applications, including broadband
access, home networking, display/projection, and digital television equipment. The Spartan-
3E family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial
cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs.
Also, FPGA programmability permits design upgrades in the field with no hardware
replacement necessary, an impossibility with ASICs.
b) Features
• Very low cost, high-performance logic solution for high-volume, consumer-oriented
applications
• Proven advanced 90-nanometer process technology
• Multi-voltage, multi-standard SelectIO™ interface pins
- Up to 376 I/O pins or 156 differential signal pairs
- LVCMOS, LVTTL, HSTL, and SSTL single-ended signal standards
- 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
- 622+ Mb/s data transfer rate per I/O
- True LVDS, RSDS, mini-LVDS, differential HSTL/SSTL differential I/O
- Enhanced Double Data Rate (DDR) support
- DDR SDRAM support up to 333 Mb/s
• Abundant, flexible logic resources
- Densities up to 33,192 logic cells, including optional shift register or distributed
RAM support
- Efficient wide multiplexers, wide logic
- Fast look-ahead carry logic
- Enhanced 18 x 18 multipliers with optional pipeline
- IEEE 1149.1/1532 JTAG programming/debug port
• Hierarchical SelectRAM™ memory architecture
- Up to 648 Kbits of fast block RAM
- Up to 231 Kbits of efficient distributed RAM
• Up to eight Digital Clock Managers (DCMs)
- Clock skew elimination (delay locked loop)
- Frequency synthesis, multiplication, division
- High-resolution phase shifting
- Wide frequency range (5 MHz to over 300 MHz)
• Eight global clocks plus eight additional clocks per each half of device, plus abundant low-
skew routing
• Configuration interface to industry-standard PROMs
- Low-cost, space-saving SPI serial Flash PROM
- x8 or x8/x16 parallel NOR Flash PROM
- Low-cost Xilinx Platform Flash with JTAG
• Complete Xilinx ISE™ and WebPACK™ development system support
• MicroBlaze™ and PicoBlaze™ embedded processor cores
• Fully compliant 32-/64-bit 33 MHz PCI support
25
• Low-cost QFP and BGA packaging options
- Common footprints support easy density migration
- Pb-free packaging options
8. 1Gb F-die DDR2-1066 SDRAM (U41-U42-U8-U9)
Samsung K4T1G084QF
a) Key Features
• JEDEC standard VDD = 1.8V ± 0.1V Power Supply
•VDDQ = 1.8V ± 0.1V
• 533MHz fCK for 1066Mb/sec/pin
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 4, 5, 6, 7
• Programmable Additive Latency: 3, 4, 5. 6
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Special Function Support
- PASR(Partial Array Self Refresh)
- 50ohm ODT
- High Temperature Self-Refresh rate enable
• Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C
• All of products are Lead-free, Halogen-free, and RoHS compliant
The 1Gb DDR2 SDRAM is organized as a 16Mbit x 8 I/Os x 8 banks, 8Mbit x 16 I/Os x 8
banks device. This synchronous device achieves high speed double-data-rate transfer rates of
up to 1066Mb/sec/pin (DDR2-1066) for general applications.
The chip is designed to comply with the following key DDR2 SDRAM features such as
posted CAS with additive latency, write latency = read latency - 1, Off-Chip Driver(OCD)
impedance adjustment and On Die Termination. All of the control and address inputs are
synchronized with a pair of externally supplied differential clocks. Inputs are latched at the
crosspoint of differential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address
40
LC-40LS340