14. I/O expansion bus specifications
The table below shows the standard bus for expanding optional
devices
Table 18
Signal name
Pin No.
Pin No.
Signal name
GND
1
41
GND
GND
2
42
GND
RDO
3
43
RD
WRO
4
44
EXWAIT
+5V
5
45
BREQ
+5V
6
46
BACK
A23
7
47
TRQ2
A22
8
48
TRQ1
A21
9
49
EXINT1
A20
10
50
EXINT0
A19
11
51
N.C.
A18
12
52
IRQ1
A17
13
53
RFSH
A16
14
54
IPLON0
A15
15
55
D7
A14
16
56
D6
A13
17
57
D5
A12
18
58
D4
A11
19
59
D3
A10
20
60
D2
A9
21
61
D1
A8
22
62
D0
A7
23
63
POFF
A6
24
64
VCKDC
A5
25
65
+12V
A4
26
66
A3
←
+24V
27
67
+24V
←
+24V
28
68
+24V
A1
29
69
A2
A0
30
70
RES
RESET
31
71
AS
OPTCS
32
72
WR
SYNC
33
73
MCRRDY1
34
74
MCRRDY2
35
75
MCR1
36
76
MCR2
37
77
–12V
38
78
GND
39
79
GND
GND
40
80
GND
15. Reset sequence
The reset sequence block diagram is shown below. Note that RESET
signal (system reset) and CKDCR signal (CKDC reset) are different
from each other.
Fig. 14
15-1. Power ON/OFF
The flow of signal processing at the time of the power supply turning
On/Off is as follows:
Table 19
<Power OFF>
Power supply
MPCA6
CPU
CKDC7
1
POFF
→
L
2
IRQ0
→
L
3
STOP
→
L
4
RESET
→
L
(System reset)
Table 20
<Power ON>
Power supply
MPCA6
CPU
CKDC7
1
POFF
→
H
2
RESET
→
H
(System reset)
The table below shows the timing chart.
Fig. 15
POFF
CKDCR
(CKDC reset)
VCC
PG
GOOD
INT0
IRQ0
STOP
RESET
(System reset)
SLIDE
SW
CKDC7
MPCA7
POWER
SUPPLY
CPU
+5V,+12V
PG GOOD
(POFF)
RESET
(System)
STOP
SHEN
SCK
MIN
10ms MIN
200ms
8 PULSE
20ms is assured when as power is off.
7
–
32
Summary of Contents for ER-A750
Page 3: ......
Page 8: ...CHAPTER2 OPTIONS 1 System configuration 2 1 ...
Page 32: ...7 2 2 Description of main LSI s 2 1 CPU HD6415108FX ...
Page 66: ...CHAPTER 8 PWB LAYOUT 1 Main PWB Side A 8 1 ...
Page 67: ...2 Main PWB Side B 8 2 ...
Page 68: ...3 Mother PWB Side A 4 CKDC PWB 8 3 ...
Page 69: ...5 Rear display PWB 6 Invator PWB 7 Noise filter PWB 8 4 ...