2) Block diagram
Fig. 2-2
P47
P46
P45
P44
P43
P42
P41/TMCI
P40
P37
P36
P35
P34
P33
BREQ
BACK
WAIT
P27/A23
P26/A22
P25/A21
P24/A20
P23/A19
P22/A18
P21/A17
P20/A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AVCC
AVSS
MD2
MD1
MD0
RES
STBY
NMI
AS
RD
HWR
LWR
RFSH
EXTAL
XTAL
E
H8/500 CPU
DTC
Serial
communication
interface x 2ch
8bit timer
16bit free running
timer x 2ch
Refresh controller
Wait state
controller
A/D convertor
Interruption controller
Clock
oscillator
Watch
dog timer
Data bus
Port 1
D
a
ta b
u
s (
L
ow
er
)
D
a
ta
bus
(
U
p
per
)
A
ddr
e
ss
bu
s
Po
rt
2
Port 5
Port 6
Port 7
Port 8
A
d
dr
e
ss
bus
X
7
–
3
Summary of Contents for ER-A750
Page 3: ......
Page 8: ...CHAPTER2 OPTIONS 1 System configuration 2 1 ...
Page 32: ...7 2 2 Description of main LSI s 2 1 CPU HD6415108FX ...
Page 66: ...CHAPTER 8 PWB LAYOUT 1 Main PWB Side A 8 1 ...
Page 67: ...2 Main PWB Side B 8 2 ...
Page 68: ...3 Mother PWB Side A 4 CKDC PWB 8 3 ...
Page 69: ...5 Rear display PWB 6 Invator PWB 7 Noise filter PWB 8 4 ...