2) Block diagram
3) Pin configuration
IOCS,IOWR,IORD
MEMCS,MEMWR,MEMRD
AB0~AB15
BHE
DB0~DB15
MPX
OSC1
OSC2
VA0~VA15
VCS0~VCS4
VWE
VD0~VD15
16bit
LCDENB
XSCL
LP
YD
WF
UD0~UD3
LD0~LD3
R1
R15
READY
RESET
MPUSEL,MPUCLK
ADDRESS BUFFER
DATA BUFFER
BASIC TIMING
GENERATING CIRCUIT
OSCILLATION
CIRCUIT
CONTROL REGISTER
DISPLAY
TIMING
CONTROL
CIRCUIT
VRAM
CONTROL
CIRCUIT
I/O
CONTROL CIRCUIT
REFRESH
ADDRESS
COUNTER
DISPLAY DATA
CONTROL
CIRCUIT
MPX
VA 3
VA2
VA 1
VA0
VWE
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB 3
DB 2
DB 1
VD 11
VD12
VD 13
VD14
VD 15
LCDENB
XSCL
L P
W F
YD
UD0
UD1
UD2
UD3
LD0
LD1
LD2
LD3
O S C1
O S C2
8 1
100
5 0
3 1
5 1
80
3 0
1
SED1351F0A
7
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22
Summary of Contents for ER-A750
Page 3: ......
Page 8: ...CHAPTER2 OPTIONS 1 System configuration 2 1 ...
Page 32: ...7 2 2 Description of main LSI s 2 1 CPU HD6415108FX ...
Page 66: ...CHAPTER 8 PWB LAYOUT 1 Main PWB Side A 8 1 ...
Page 67: ...2 Main PWB Side B 8 2 ...
Page 68: ...3 Mother PWB Side A 4 CKDC PWB 8 3 ...
Page 69: ...5 Rear display PWB 6 Invator PWB 7 Noise filter PWB 8 4 ...