No.
Pin No.
Pin name
I/O
Pin
ER-A750
Description
54
28
TRQ1-
O
3S
TRQ1
TIMER IRQ signal (RS-232)
55
29
TRQ2-
O
3S
NC
TIMER IRQ signal (INLINE)
56
11
D0
I/O
IOU
D0
DATA BUS (MAIN)
57
12
D1
I/O
IOU
D1
58
13
D2
I/O
IOU
D2
59
14
D3
I/O
IOU
D3
60
16
D4
I/O
IOU
D4
61
17
D5
I/O
IOU
D5
62
18
D6
I/O
IOU
D6
63
19
D7
I/O
IOU
D7
64
61
DB0
I/O
IOU
DB0
DATA BUS (USART)
65
62
DB1
I/O
IOU
DB1
66
63
DB2
I/O
IOU
DB2
67
64
DB3
I/O
IOU
DB3
68
66
DB4
I/O
IOU
DB4
69
67
DB5
I/O
IOU
DB5
70
68
DB6
I/O
IOU
DB6
71
69
DB7
I/O
IOU
DB7
72
21
A0
I
I
A0
ADDRESS BUS (MAIN)
73
22
A1
I
I
A1
74
23
A2
I
I
A2
75
24
A3
I
I
A3
76
25
A4
I
I
A4
77
26
A5
I
I
A5
78
10
OPTCS-
I
I
OPTCS-
OPTION CHIP SELECT (from MPCA7)
79
31
RDO-
I
I
RDO-
READ signal (from MPCA7)
80
30
WRO-
I
I
WRO-
WRITE signal (from MPCA7)
81
9
RES-
I
IS
RES-
RESET signal (from MAIN)
82
34
R-
O
O
RDH
READ signal (To USART)
83
37
W-
O
O
WRH
WRITE signal (To USART)
84
51
RES
O
O
RES USART
RESET signal (To USART)
85
92
X1
O
NC
cillation circuit
86
91
X2
I
#
87
53
XOUT
O
O
CLK
USART
Clock for USART
88
8
TRCK
O
O
NC
T/R clock for 1CH USART
89
35
AB0
O
O
AH0
Address bus for USART
90
33
AB1
O
O
AH1
91
85
USICH
I
ISC
GND
UNIT3 USART 1CH/2CH select
92
50
PX
O
NC
Power source clock
93
39
VCC
+5V
94
89
VCC
+5V
95
15
GND
GND
96
40
GND
GND
97
65
GND
GND
98
90
GND
GND
99
49
RTS0-
O
O
RTS1-
RS-232 control signal RTS- output
100
44
RTS1-
O
O
RTS2-
ICU : CMOS level input (internal pullup resistor)
O
: Output
IS
: TTL level input (internal schmit circuit)
ISC : CMOS level input (internal schmit circuit)
3S
: Three state output
IOU : I/O port (internal pullup resistor)
7
–
12
Summary of Contents for ER-A750
Page 3: ......
Page 8: ...CHAPTER2 OPTIONS 1 System configuration 2 1 ...
Page 32: ...7 2 2 Description of main LSI s 2 1 CPU HD6415108FX ...
Page 66: ...CHAPTER 8 PWB LAYOUT 1 Main PWB Side A 8 1 ...
Page 67: ...2 Main PWB Side B 8 2 ...
Page 68: ...3 Mother PWB Side A 4 CKDC PWB 8 3 ...
Page 69: ...5 Rear display PWB 6 Invator PWB 7 Noise filter PWB 8 4 ...