SGS ATES Z80, Instruction Set

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B 000
C 001
DOlO
E 011
H 100
L 101
A 111
A logical AND operation, bit by bit, is performed
between the byte specified by the s operand and the b y te
contained in the Accumulator; the result is stored in
the Accumulator.
INSTRUCTION H CYCLES T STATES 4 11HZ E . T.
AND r 1
4
1 . 00
AND
n
2
7(4,3)
1 . 75
AND
(HL)
2
7(4,3)
1 . 75
AND (IX+d) 5 19(4,4,3,5,3) 4.75
AND (I X +d) 5 19(4,4,3,5,3) 4.75
Condition Bits Affected:
Set if result is negative;
reset otherwise
Set if result is zero;
reset otherwise
Se
t
Set if parity even;
reset otherwise
Reset
Reset
H:
P / V:
If the B register contains 7BH (01111011) and the
Accumulator contains C3H (11000011) after the execut io n
of