SGS ATES Z80 Instruction Set Download Page 90 | Manualshive

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background image

B

000

C

001

DO

l

O

E

0

1

1

H

100

L

101

A

111

The

s operand,

along

with

the

Carry

Flag

("C"

in

the

F

register)

is

added

to

t

he

contents

of

the

Accumulator,

and

the

result

is

stored

in

the

Accumulator.

INSTRUCTION

M

CYCLES

T

STATES

4 HHZ

E.T.

ADC

A,r

1

4

1.00

ADC

A,n

2

7(4,3)

1

.

75

ADC

A, (HL)

2

7(4,3)

1

.

75

ADC

A, (IX+d)

5

19(4,4,3,5,3)

4.75

ADC

A,(IY+d)

5

19(4,4,3,5,3)

4.75

Condi tion

Bits

Affected:

Set

if

result

is

negative;

reset

otherwise

Set

if

resul

t

is

zero;

reset

otherwise

Set

if

carry

from

Bit

3;

reset

otherwise

Set

if

overflow

;

reset

otherwise

Re se t

Set

if

carry

from

Bit

7;

reset

otherwise

If

the

Accumulator

contains

16H,

the

Carry

Flag

is

s

e

t,

the

HL

register

pair

contains

6666H,

and

address

6666

H

contains

10H,

after

the

execution

of

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Summary of Contents for ATES Z80

Page 1: ......

Page 2: ...the Z80 CPU is not intended exclusively as an application support for the device itself but forms the second part of the instruction manual for SGS ATES CLZ80 microcomputer which is based on the Z80 m...

Page 3: ...h M cycle For exanple is Total indicates that the instruction consists of 2 nachine cycles ihe first cycle contains 4 clock periods T States The second cycle contains 3 clock periods for a total of 7...

Page 4: ...SEARCH GROUP 55 2 3 8 BIT ARITHMETIC AND LOGICAL GROUP 79 2 4 GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS 111 2 5 16 BIT ARITHMETIC GROUP 127 2 6 ROTATE AND SHIFT GROUP 145 2 7 BIT SET RESET AN...

Page 5: ......

Page 6: ...Juanlurn c cc r 11 SoJt 391262 Jr ml tOl...

Page 7: ...any other register r Note r r identifies any of the registers A B C D E li or L assembled as follows in the object code A 111 B 000 COOl DOlO E 011 li 100 L 101 If the li register contains the number...

Page 8: ...a o r 01 I in 1 The eight bit integer n is loaded into any register r where r identifies register A n C D E H or L assembled as follows in the object code Register r A 111 B 000 C 001 D 010 E 011 H 10...

Page 9: ...loaded into register r where r identifies register A B C D E H or L assembled as follo ls in the object code A 111 BODO COOl DOlO E 011 H 100 L 101 If register pair HL contains the number 7SA1H and me...

Page 10: ...egister IX summed with a displacement integer d is loaded into register r where r identifies register A B C D E H or L assembled as follows in the object code Register r A III B 000 C 001 D 010 E 011...

Page 11: ...will cause the calculation of the sum 25AFH 19H which points to memory location 25C8H If this address contains byte 39H the ins truction will result in register B also containing 39H...

Page 12: ...perand IY d the contents of the Index Register IY sUQQed with a displacement integer d is loaded into register r where r identifies register A n C D E H or L assembled as follows in the object code A...

Page 13: ...contains the number 2SAFll the instruction will cause the calculation of the sum 2SAFll 19H which points to memory location 2SC8H If this address contains byte 39H the instruction will result in regis...

Page 14: ...he contents of the ilL register pair The symbol r identifies register A B C D E il or L assembled as follows in the object code A 111 B 000 COOl DOlO E all H 100 L 101 If the contents of register pair...

Page 15: ...ed into the memory address specified by the contents of Index Register IX summed with d a two s complement displacement integer The symbol r identifies register A B C D E H or L assembled as follows i...

Page 16: ...If the C register contains the byte lCH and the Index Register IX contains 3100H then the instruction will perform the sum 3100H 6H and will load lCH into memory location 3106H...

Page 17: ...r are loaded into the memory address specified by the sum of the contents of the Index Register IY and d a two s complenent displacenent integer The symbol r is specified according to the following t...

Page 18: ...If the C register contains the byte 48H and the Index Register IY contains 2AIIH then the instruction will perform the sum 2AIIH 4H and will load 48H into memory location 2A15...

Page 19: ...LD HLJ I0 0 a 0 I 36 I In 1 Integer n is loaded into the memory address specified by the contents of the HL register pair will result in the memory location 4444H containing the byte 281I...

Page 20: ...oaded into the memory address specified by the sum of the contents of the Index Register IX and the two s complement displacement operand d If the Index Register IX contains the number 219AH the instr...

Page 21: ...a a a I 36 1 I 1 In I Integer n is loaded into the memory location specified by the contents of the Index Register sUDDed with a displacement integer d If the Index Register IY contains the number A9...

Page 22: ...he memory location specified by the contents of the BC register pair are loaded into the AccuJ lulator If the BC register pair contains the number 4747H and J leJ lory address 4747H contains the byte...

Page 23: ...ntents of the memory location specified by the reg ster pair DE are loaded into the Accumulator If the DE register pair contains the number 30A2H and memory address 30A2H contains the byte 22H then th...

Page 24: ...In 1 The contents of the memory location specified operands nn are loaded into the Accumulator n operand is the low order byte of a two byte address by the The first memory If the contents of nn is n...

Page 25: ...The contents of the Accumulator are loaded into the memory location specified by the contents of the register pair BG If the Accumulator contains 7AH and the BG register pair contains 1212H the instr...

Page 26: ...A The contents of the Accuflulator are loaded into the memory location specified by the DE register pair If the contents of register pair DE are ll28H and the Accuculator contains byte AOH the instru...

Page 27: ...ontents of the Accumulator are loaded into the memory address specified by the operands nn The first n operand in the assembled object code above is the low order byte of nn If the contents of the Acc...

Page 28: ...ctor Register I are loaded into the Accumulator Set if I Reg is negative reset otherwise Set if I Reg is zero reset otherwise Reset Contains contents of IFF2 Reset Not affected II P V N C If the Inter...

Page 29: ...Register R are loaded into the Accumulator Set if R Reg is negative reset otherwise Set if R Reg is zero reset otherwise Re se t Contains contents of IFF2 Re se t Not affected H P V N C If the Memory...

Page 30: ...LD A I a a I ED I a a a a I 47 The contents of the Accunulator are loaded into the Interrupt Control Vector Register I If the Accumulator contains the number B1R after the instruction...

Page 31: ...LD R A I a a I ED I a a a I 4F The contents of the Accumulator are loaded into the Memory Refresh register R If the Accumulator contains the number B4H after the instruction...

Page 32: ......

Page 33: ...two byte integer nn is loaded into the dd register pair where dd defines the BC DE HL or SP register pairs assembled as follows in the object code BC 00 DE 01 HL 10 SP 11 The first n operand in the a...

Page 34: ...LD IX I a a I DO Ia a a a a a I 21 I in I I in I Integer nn is loaded into the Index Register IX The first n operand in the assembled object code above is the low order byte...

Page 35: ...LD IY 11 1 1 0 1 FD I 0 0 0 0 0 0 1 I 21 I I In I I 1 I In I I 1 Integer nn is loaded into the Index Register IY The first n operand in the assembled object code above is the low order byte...

Page 36: ...on of register pair HL register L and the contents of the next highest memory address nn l are loaded into the high order portion of ilL register H The first n operand in the assembled object code abo...

Page 37: ...register pair dd and the contents of the next highest memory address nn l are loaded into the high order portion of dd Register pair dd defines BC DE HL or SP register pairs assembled as follows in t...

Page 38: ...If Address 2130ll contains 65ll and address 2131H contains 78ll after the instruction...

Page 39: ...the low order portion of Index Register IX and the contents of the next highest menory address nn l are loaded into the high order portion of IX The first n operand in the assembled object code above...

Page 40: ...10 order portion of Index Register IY and the content the next highest cemory address nn l are loaded il the high order portion of IY The first n operand il assembled object code above is the low ord...

Page 41: ...s nn and the contents of the high order portion of ilL register II are loaded into the next highest memory address nn l The first n operand in the assembled object code above is the low order byte of...

Page 42: ...loaded into memory address nn the upper byte is loaded into memory address nn 1 Register pair dd defines either BC DE HL or SP assembled as follows in the object code Pair dd BC 00 DE 01 HL 10 SP 11...

Page 43: ...If register pair BG contains the number 4644H the instruc tion will result in 44H in memory location lOOOH and 46H in memory location lOOlH...

Page 44: ...to memory address nn the upper order byte is loaded into the next highest address nn l The first n operand in the assembled object code above is the low order byte of nn If the Index Register IX conta...

Page 45: ...o memory address nn the upper order byte is loaded into memory location nn l The first n operand in the assembled object code above is the low order byte of nn If the Index Register IY contains 4174H...

Page 46: ...LD SP HL The contents of the register pair HL are loaded into the Stack Pointer SP If the register pair ilL contains 442EH after the instruction...

Page 47: ...LD SP IX I 0 a I DO I a a 1 I F9 The two byte contents of Index Register IX are loaded into the Stack Pointer SP If the contents of the Index Register IX are 98DAH after the instruction...

Page 48: ...LD SP IY 11 a I FD 11 a a I F9 The two byte contents of Index Register IY are loaded into the Stack Pointer SP If Index Register IY contains the integer A227U after the instruction...

Page 49: ...w specified by the SP then decrements the SP again and loads the low order byte of qq into the memory location corresponding to this new address in the SP The operand qq means register pair BC DE HL o...

Page 50: ...rst decrements the SP and loads the high order byte of IX into the memory address now specified by the SP then decrements the SP again and loads the low order byte into the memory location correspondi...

Page 51: ...st decrecents the SP and loads the high order byte of IY into the memory address now specified by the SP then decrements the SP again and loads the low order byte into the ce ory location correspondin...

Page 52: ...instruction first loads into the low order portion of qq the byte at the memory location corresponding to the contents of SP then SP is incremented and the contents of the corresponding adjacent menor...

Page 53: ...the Stack Pointer contains 1000H memory location 1000H contains 55H and location 1001H contains 33H the instruction will result in register pair HL containing 3355H and the Stack Pointer containing 10...

Page 54: ...the low order portion of IX the byte at the memory location corresponding to the contents of SP then SP is incremented and the contents of the corresponding adjacent memory location are loaded into t...

Page 55: ...ow order portion of IY the byte at the memory location corresponding to the contents of SP then SP is incremented and the contents of the corresponding adjacent Qemory location are loaded into the hig...

Page 56: ......

Page 57: ...and HL are exchanged If the content of register pair DE is the number 2822H and the content of the register pair HL is number 499AH after the instruction the content of register pair DE will be 499AH...

Page 58: ...are exchanged Note register pair AF consists of registers A and F If the content of register pair AF is number 9900H and the content of register pair AF is number 5944H after the instruction the cont...

Page 59: ...If the contents of register pairs BC DE and HL are the numbers 445AH 3DA2H and 88590 respectively and the contents of register pairs BC DE and HL are 0988H 9300H and OOE7H respectively after the inst...

Page 60: ...ext highest memory address SP l If the HL register pair contains 7012ll the SP register pair contains 8856H the memory location 8856H contains the byte IlH and the memory location 8857H contains the b...

Page 61: ...is exchanged with the next highest memory address SP l If the Index Register IX contains 3988H the SP register pair contains olooH the memory location olooH contains the byte 90H and memory location...

Page 62: ...s exchanged with the next highest memory address SP l If the Index Register IY contains 3988H the SP register pair contains 0100ll the memory location 0100H contains the byte 90ll and memory location...

Page 63: ...the contents of the HL register pair to the memory location addressed by the contents of the DE register pair Then both these register pairs are incremented and the BC Byte Counter register pair is de...

Page 64: ...s the byte BSH the DE register pair contains 2222H the memory location 2222H contains byte 66ll and the BC register pair contains 7H then the instruc tion will result in the following contents in regi...

Page 65: ...airs are incremented and the BC Byte Counter register pair is decremented If decreoenting causes the BC to go to zero the instruction is terminated If BC is not zero the progra counter is decremented...

Page 66: ...DE register pair contains 2222H the BC register pair contains 0003H and memory locations have these contents llllH 1112H l113H 88H 36ll A5H 2222ll 2223H 2224H 66H 59H C5H the contents of register pai...

Page 67: ...eidressed by the contents of the HL register pair to the memory location addressed by the contents of the DE register pair Then both of these register pairs including the BC Byte Counter register pai...

Page 68: ...the byte 88H the DE register pair contains 2222H memory location 2222H contains byte 66H and the BC register pair contains 7H then the in str uc tion will result in the following contents in register...

Page 69: ...Byte Counter are decremented If decrementing causes the BC to go to zero the instruction is ter inated If BC is not zero the progra counter is decre ented by 2 and the instruction is repeated Note tha...

Page 70: ...C register pair contains 0003H and memory locations have these contents l114H l113H l112H A5H 36H SSH 2225Il 2224H 2223H C5Il 59H 66H the contents of register pairs and memory locations will be HL lll...

Page 71: ...HL is incremented and the Byte Counter register pair BC is decremented Set if result is negative reset otherwise Set if A llL reset otherwi5e Set ifthere is a borrow and reset otherwise Set if BC L fO...

Page 72: ...contain OOOOH the HL register pair will contain 1112H the Z flag in the F register will be set and the P V flag in the F register will be reset There will be no effect on the contents of the Accumula...

Page 73: ...register pair BC is decremented If decrementing causes the BC to go to zero or if A HL the instruction is terminated If BC is not zero and A HL the program counter is decremented by 2 and the instruc...

Page 74: ...d If the ilL register pair contains 1111il the Accumulator contains F3il the Byte Counter contains On07H and memory locations have these contents 111111 52il 111211 OOil 1113H F3il the contents of reg...

Page 75: ...et The ilL and the Byte Counter register pair BC are decremented Set if result is negative reset otherwise Set if A HL reset otherwise Set if there is a borrow and reset otherwise Set if BC l oio rese...

Page 76: ...contain OOOOH the HL register pair will contain IIIOH the Z flag in the F register will be set and the P V flag in the F register will be reset There will be no effect on the contents of the Accumula...

Page 77: ...pairs are decremented If decrementing causes the BC to go to zero or if A HL the instruction is terminated If BC is not zero and AI HL the program counter is decremented by 2 and the instruction is re...

Page 78: ...cted If the HL register pair contains 1118H the Accumulator contains F3H the Byte Counter contains 0007H and memory locations have these contents 1118H 1117H 1116H 52H OOH F3H the contents of register...

Page 79: ......

Page 80: ......

Page 81: ...identifies the registers A B C D E H or L assembled as follows in the object code Register r A 111 B 000 C 001 D 010 E 011 H 100 L 101 Set if result is negative reset otherwise Set if result is zero r...

Page 82: ...If the contents of the Accumulator are 44H and the contents of register Care IlH after the execution of...

Page 83: ...lts are stored in the Accumulator Set if result is negative reset otherwise Set if result is zero reset otherwise Set if carry from Bit 3 reset otherwise Set if overflow reset otherwise Reset Set if c...

Page 84: ...T 1 75 Condi tion Bits Affected S Set if result is negative reset otherwise Z Set if result is zero reset otherwise H Se t if carry from Bit 3 reset otherwise P V Set if overflow reset otherwise N Re...

Page 85: ...n added to the contents of the Accumulator and the result is stored in the Accumulator Set if result is negative reset otherwise Set if result is zero reset otherwise Set if carry from Bit 3 reset oth...

Page 86: ...10050 is 220 after the execution of ADD A IX SH the contents of the Accumulator will be 33H...

Page 87: ...en added to the contents of the Accumulator and the result is stored in the AccuQulator Set if result is negative reset otherwise Set if result is zero reset otherwise Set if carry from Bit 3 reset ot...

Page 88: ......

Page 89: ...r the analogous ADD instruction These various possible opcode operand combinations are assembled as follows in the object code 11 0 0 0 1 r I I a a 0 I CE in 1 I a a a 0 I 8E I 0 a I DD I a a a 0 8E I...

Page 90: ...3 1 75 ADC A HL 2 7 4 3 1 75 ADC A IX d 5 19 4 4 3 5 3 4 75 ADC A IY d 5 19 4 4 3 5 3 4 75 Condi tion Bits Affected Set if result is negative reset otherwise Set if result is zero reset otherwise Set...

Page 91: ...These various possible opcode operand combinations are assembled as follows in the object code I 0 a a r I a a 0 06 1 In l I a a a 0 96 11 1 0 1 1 1 0 1 DO I a a a 0 96 I 1 a 1 FD I 0 0 0 a I 96 1 1...

Page 92: ...0 SUB n 2 7 4 3 1 75 SUB ilL 2 7 4 3 1 75 SUB IX d 5 19 4 4 3 5 3 4 75 SUB IY d 5 19 4 4 3 5 3 4 75 Condition Bits Affected Set if result is negative reset otherwise Set if result is zero reset otherw...

Page 93: ...fined for the analogous ADD instructions These various possible opcode operand combinations are assembled as follows in the object code 11 a a r 1 11 0 0 I 1 In I 1 0 0 1 1 a 0 I a 0 0 I d I I 11 0 I...

Page 94: ...3 1 75 SBC A HL 2 7 4 3 1 75 SBC A IX d 5 19 4 4 3 5 3 4 75 SBC A IY d 5 19 4 4 3 5 3 4 75 Condition Bits Affected Set if result is negative reset other iise Set if result is zero reset otherwise Set...

Page 95: ...instructions These various possible opcode operand combinations are assembled as follows in the object code 1 a a a r 1 a a 0 E6 In a a 0 0 A6 1 a a DO a a a 0 A6 1 0 1 FD 0 0 0 0 1 A6 I r identifies...

Page 96: ...STRUCTION H CYCLES T STATES 4 11HZ E T AND r 1 4 1 00 AND n 2 7 4 3 1 75 AND HL 2 7 4 3 1 75 AND IX d 5 19 4 4 3 5 3 4 75 AND IX d 5 19 4 4 3 5 3 4 75 Condition Bits Affected Set if result is negative...

Page 97: ...tions These various possible opcode operand conbinations are assembled as follows in the object code 0 o r 1 0 0 I F6 in I 0 1 0 0 I 86 1 1 0 1 1 1 0 1 DO 1 0 0 a 86 I l I 1 1 0 1 FD I a a 0 B6 I r id...

Page 98: ...STRUCTION 1 1 CYCLES T STATES 4 MHZ E T OR r 1 4 1 00 OR n 2 7 4 3 1 75 OR HL 2 7 4 3 1 75 OR IX d 5 19 4 4 3 5 3 4 75 OR IY d 5 19 4 4 3 5 3 4 75 Condi tion Bits Affected Set if result is negative re...

Page 99: ...ions These various possible opcode operand combinations are assembled as follows in the object code I a a l r 1 1 a 0 I EE 1 In 1 I a a 0 I AE I a a I DO I a a a I AE 1 1 1 a I FD I a a 0 I AE 1 1 r i...

Page 100: ...d in the Accumulator INSTRUCTION M CYCLES T STATES 4 MHZ E T XOR r 1 4 1 00 XOR n 2 7 4 3 1 75 XOR HL 2 7 4 3 1 75 XOR IX d 5 19 4 4 3 5 3 4 75 XOR IY d 5 19 4 4 3 5 3 4 75 Condition Bits Affected Set...

Page 101: ...DD instructions These various possible opcode operand combinations are assembled as follows in the object code o r 1 a I FE In 1 1 a a I BE a a I DD 1 a a I BE I 1 a I FD I 0 aI BE 1 1 r identifies re...

Page 102: ...2 7 4 3 1 75 CP IX d 5 19 4 4 3 5 3 4 75 CP IY d 5 19 4 4 3 5 3 4 75 Set if result is negative reset otherwise Set if result is zero reset otherwise Set ifthere is a borrow and reset otherwise Set if...

Page 103: ...ect code Register r A 111 B 000 C 001 D 010 E 011 H 100 L 101 M CYCLES T STATES 4 4 HHZ E T 1 00 Condition Bits Affected Set if result is negative reset otherwise Set if result is zero reset otherwise...

Page 104: ...If the contents of register Dare 280 after the execution of...

Page 105: ...Set if result is negative reset otherwise Set if result is zero reset otherwise Set if carry from Bit 3 reset otherwise Set if HL was 7FH before operation reset otherwise Re se t Not Affected If the c...

Page 106: ...o s complement displacement integer d to point to an address in memory The contents of this address are then incremented Set if result is negative reset otherwise Set if result is zero reset otherwise...

Page 107: ...If the contents of the Index Register pair IX are 2020H and the Demory location 2030H contains byte 348 after the execution of...

Page 108: ...o s cOQplement displacement integer d to point to an address in memory The contents of this address are then incremented Set if result is negative reset otherwise Set if result is zero reset otherwise...

Page 109: ...If the contents of the Index Register pair IY are 2020H and the memory location 2030H contain byte 34H after the execution of...

Page 110: ...nalogous INC instructions These various possible opcode operand combinations are assembled as follows in the object code o a r a 1 o 0 1 1 0 1 0 1 1 0 0 0 0 o 0 1 1 0 1 0 1 d r identifies registers B...

Page 111: ...C IX d 6 23 4 4 3 5 4 3 5 75 DEC IY d 6 23 4 4 3 5 4 3 5 75 Condition Bits Affected Set if result is negative reset otherwise Set if result is zero reset otherwise Set ifthere is a borrow and re set o...

Page 112: ......

Page 113: ...n performed HEX HEX VALUE VALUE NUHBER C IN 11 IN ADDED C BEFORE UPPER BEFORE LOWER TO AFTER OPERATION DAA DIGIT DAA DIGIT BYTE DAA bit b it 7 4 3 0 0 0 9 0 0 9 00 0 0 0 8 0 A F 06 0 0 0 9 1 0 3 06 0...

Page 114: ...See instruction If an addition operation is performed between 15 BCD and 27 BCD simple decimal arithmetic gives this result 15 27 42 But yhen the binary representations are added in the Accumulator a...

Page 115: ...lator register A are inverted l s complement Condition Bits Affected S No t affected Z Not affected H Se t P V Not affected N Set C No t affected Example If the contents of the Accumulator are 1011 01...

Page 116: ...cting the contents of the Accumulator from zero Note that 80H is left unchanged Set if result is negative reset otherwise Set if result is zero reset otherwise Set ifthere is a borrow and reset otherw...

Page 117: ...Example If the contents of the Accumulator are...

Page 118: ...CCF S z H P V H c Not affected Not affected Previous carry will be copied Not affected Reset Set if CY was 0 before operation reset otherwise...

Page 119: ...SCF S z H P V N C Not affected Not affected Rese t Not affected Re se t Set...

Page 120: ...NOP Operation Format Opcode NOP Description CPU perforos no operation during this machine cycle M CYCLES 1 T STATES 4 Condition Bits Affected...

Page 121: ...HALT The HALT instruction suspends CPU operation until a subsequent interrupt or reset is received While in the halt state the processor will execute NOP s to maintain memory refresh logic...

Page 122: ...enable flip flops IFFl and IFF2 Note that this instruction disables the maskable interrupt during its execution the maskable interrupt is disabled until it is subsequently re enabled by an EI instruc...

Page 123: ...pt by setting the interrupt enable flip flops IFFl and IFF2 Note that this instruction disables the maskable interrupt during its execution the maskable interrupt is enabled The CPU will now respond t...

Page 124: ...1M o I 0 a I ED 10 1 0 0 0 1 1 0 I 46 The 1M 0 instruction sets interrupt mode O In this mode the interrupting device can insert any instruction on the data bus and allow the CPU to execute it...

Page 125: ...1M 11 0 a I ED I0 0 0 a I 56 The 1M instruction sets interrupt mode 1 In this mode the processor will respond to an interrupt by executing a restart to location 0038H...

Page 126: ...rrupt mode 2 This mode allows an indirect call to any location in memory With this mode the CPU forms a 16 bit memory address The upper eight bits are the contents of the Interrupt Vector Register I a...

Page 127: ......

Page 128: ......

Page 129: ...nts of regi pair ilL and the result is stored in ilL Operand i specified as follows in the assembled object code Register Pair ss BC 00 DE 01 ilL 10 SP 11 Not affected Not affected Set if carry out of...

Page 130: ...If register pair HL contains the integer 42428 and register pair DE contains IlllH after the execution of...

Page 131: ...in the F register to the contents of register pair HL and the result is stored in HL Operand ss is specified as follows in the assembled object code Register Pair ss BC 00 DE 01 HL 10 SP 11 Set if res...

Page 132: ...If the register pair BC contains 2222H register pair HL contains 5437H and the Carry Flas is set after the execution of...

Page 133: ...he F register are subtracted from the contents of register pair ilL and the result is stored in ilL Operand ss is specified as follows in the assembled object code Register Pair ss BC 00 DE 00 ilL 10...

Page 134: ...If the contents of the HL register pair are 9999H the contents of registeT pair DE are 11118 and the Carry Flag is set after the execution of...

Page 135: ...dded to the contents of the Index Register IX and the results are stored in IX Operand pp is specified as follows in the assembled object code Register Pair BC 00 DE 01 IX 10 SP 11 Not affected Not af...

Page 136: ...If the contents of Index Register IX are 333H and the contents of register pair Be are 5555H after the execution of...

Page 137: ...ed to the contents of Index Register IY and the result is stored in IY Operand rr is specified as follows in the assembled object code Register Pair rr BC 00 DE 01 IY 10 SP 11 Not affected Not affecte...

Page 138: ...If the contents of Index Register IY are 333H and the contents of register pair Be are SSSH after the execution of...

Page 139: ...DE HL or SP are increnented Operand ss is specified as follows in the assembled object code i egister Pair ss BC 00 DE 01 ilL 10 SP 11 M CYCLES 1 T STATES 6 4 MHZ E T 1 SO Condi tion Bits Affected No...

Page 140: ...INC x 11 0 a I DO I0 a a a a I 23 If the Index Register IX contains the integer 3300H after the execution of...

Page 141: ...INC IY I 1 0 1 I FD I 0 a a a a I 23 If the contents of the Index Register are 2977H after the execution of...

Page 142: ...airs BC DE HL or SP are decremented Operand ss is specified as follows in the assembled object code Pair ss BC 00 DE 01 HL 10 SP 11 11 CYCLES 1 T STATES 6 4 HIlZ E T 1 50 Condition Bits Affected None...

Page 143: ...DEe IX 1 1 0 1 1 1 0 1 I DO I0 0 1 0 1 0 1 I 2B If the contents of Index Register IX are 2006ll after the execution of...

Page 144: ...DEe IY I 1 0 I FD I 0 a a a I 28 If the contents of the Index Register IY are 7649H after the execution of...

Page 145: ......

Page 146: ......

Page 147: ...previous content of bit 1 is moved to bit 2 this pattern is continued throughout the register The content of bit 7 is copied into the Carry Flag C flag in register F and also into bit O Bit 0 is the l...

Page 148: ...Example If the contents of the Accumulator are...

Page 149: ...s pattern is continued throughout the register The content of bit 7 is copied into the Carry Flag C flag in register F and the previous content of the Carry Flag is copied into bit O Bit 0 is the leas...

Page 150: ...If the contents of the Accumulator and the Carry Flag are the contents of the Accumulator and the Carry Flag will be...

Page 151: ...evious content of bit 6 is copied into bit 5 this pattern is continued throughout the register The content of bit 0 is copied into bit 7 and also into the Carry Flag C flag in register F Bit 0 is the...

Page 152: ...the contents of the Accumulator and the Carry Flag will be...

Page 153: ...t 6 is copied into bit 5 this pattern is continued throughout the register The content of bit 0 is copied into the Carry Flag C flag in register F and the previous content of the Carry Flag is copied...

Page 154: ...If the contents of the Accumulator and the Carry Flag are the contents of the Accumulator and the Carry Flag will be...

Page 155: ...into bit 1 the previous content of bit 1 is copied into bit 2 this pattern is continued throughout the register Ihe content of bit 7 is copied into the Carry Flag C flag in register F and also into b...

Page 156: ...Set if result is negative reset othervlise Set if result is zero reset otherwise Re se t Set if parity even reset otherwise Re se t Data from Bit 7 of source register ll P V...

Page 157: ...e previous content of bit 1 is copied into bit 2 this pattern is continued throughout the byte The content of bit 7 is copied into the Carry Flag C flag in register F and also into bit O Bit 0 is the...

Page 158: ...If the contents of the ilL register pair are 2828H and the contents of memory location 2828H are the contents of memory location 2828il and the Carry Flag will be...

Page 159: ...teger d are rotated left the contents of bit 0 is copied into bit 1 the previous content of bit 1 is copied into bit 2 this pattern is continued throughout the byte The content of bit 7 is copied into...

Page 160: ...If the contents of the Index Register IX are 1000H and the contents of memory location 1022 are the contents of menory location 1002H and the Carry Flag v ill be...

Page 161: ...nteger d are rotated left the content of bit 0 is copied into bit 1 the previous content of bit 1 is copied into bit 2 this process is continued throughout the byte The content of bit 7 is copied into...

Page 162: ...If the contents of the Index Register IY are lOOOH and the contents of memory location l002H are the contents of memory location l002H and the Carry Flag illbe...

Page 163: ...d as defined for the analogous RLe instructions These various possible opcode operand combinations are specified as follows in the assembled object code 1 1 0 0 1 0 I CB 0 a 0 a 7 r 1 a a 1 a CB a a a...

Page 164: ...f bit 0 is copied into bit 1 the previous content of bit 1 is copied into bit 2 this pattern is continued throughout the byte The content of bit 7 is copied into the Carry Flag C flag in register F an...

Page 165: ...Set if result is negative reset otherwise Set if result is zero reset otherwise Rese t Set if parity even reset otherwise Re se t Data from Bit 7 of source register Ii P V...

Page 166: ...or IY d as defined for the analogous RLC instructions These various possible opcode operand combinations are specified as follows in the assembled object code 1 0 0 0 I CB 0 0 0 0 1 r 1 0 0 0 CB o 0...

Page 167: ...ight the content of bit 7 is copied into bit 6 the previous content of bit 6 is copied into bit 5 this pattern is continued throughout the byte The content of bit 0 is copied into the Carry Flag C fla...

Page 168: ...Set if result is negative reset otherwise Set if result is zero reset otherwise Re se t Set if parity even reset otherwise Re se t Data from Bit 0 of source register H P V...

Page 169: ...is any of r HL IX d or IY d as defined for the analogous RLC instructions These various possible opcode operand combinations are specified as follows in the assembled object code 1 1 0 0 1 0 1 1 CB o...

Page 170: ...s copied into bit 6 the previous content of bit 6 is copied into bit 5 this pattern is continued throughout the byte The content of bit a is copied into the Carry Flag C flag in register F and the pre...

Page 171: ...rwise Re se t Set if parity is even reset otherwise Re se t Data from Bit 0 of source register H P V If the contents of the HL register pair are 4343H and the contents of nemory location 4343H and the...

Page 172: ...r IY d as defined for the analogous RLC instructions These various possible opcode operand conbinations are specified as follows in the assembled object code 1 1 0 0 1 0 1 1 0 r 1 1 0 0 1 0 1 1 o 0 1...

Page 173: ...contents of operand m bit 0 is reset the previous content of bit 0 is copied into bit 1 the previous content of bit 1 is copied into bit 2 this pattern is continued throughout the content of bit 7 is...

Page 174: ...Affected S Se t if result is negative reset otherwise z Se t if result is zero reset otherwise H Re se t p V Se t if parity is even reset otherwise N Reset C Data from Bit 7 Example If the contents of...

Page 175: ...d as defined for the analogous RLC instructions These various possible opcode operand combinations are specified as follows in the assembled object code 1 a a a I CB a a a l r 1 1 1 0 0 1 0 1 1 CB 0...

Page 176: ...tents of operand m the content of bit 7 is copied into bit 6 he previous content of bit 6 is copied into bit 5 this pattern is continued throughout the byte The content of bit 0 is copied into the Car...

Page 177: ...t otherwise Re se t Set if parity is even reset otherwise Re se t Data fro Bit 0 of source register H p v If the contents of the Index Register IX are lOOOH and the contents of me ory location l003H a...

Page 178: ...fined for the analogous RLC instructions These various possible opcode operand combinations are specified as ollows in the assembled object code 11 0 0 0 I CB 10 0 1 1 1 r 1 I 0 0 0 1 I CB I 0 0 1 1 1...

Page 179: ...and m are shifted right the content of bit 7 is copied into bit 6 the content of bit 6 is copied into bit 5 this pattern is continued throughout the byte The content of bit 0 is copied into the Carry...

Page 180: ...Set if result is negative reset otherwise Set if result is zero reset otherwise Re se t Set if parity is even reset otherwise Re se t Data from Bit 0 of source register H P V...

Page 181: ...r register A and the previous contents of the low order four bits of the Accumulator are copied into he low order four bits of memory location IlL The contents of the high order bits of the Accumulato...

Page 182: ...If the contents of the HL register pair are SOOOH and the contents of the Accumu ator and memory location SOOOH are the contents of the Accumulator and memory location SOOOH will be...

Page 183: ...5 and 4 of location ilL and the previous contents of the high order four bits of ilL are copied into the low order four bits of ilL The contents of the high order bits of the Accumulator are unaffecte...

Page 184: ...If the contents of the HL register pair are SOOOH and the contents of the Accu ulator and memory location SOOOH are the contents of the Accumulator and menory location 5000H will be...

Page 185: ......

Page 186: ......

Page 187: ...of the indicated bit within the indicated register Operands b and r are specified as follows in the assenbled object code Bit Tested b R g_ e r a 000 B 000 1 001 C 001 2 010 D 010 3 all E all 4 100 II...

Page 188: ...If bit 2 in register B contains 0 after the execution of the Z flag in the F register will contain 1 and bit 2 in register B will remain O Bit 0 in register B is the least significant bit...

Page 189: ...dicated bit within the contents of the ilL register pair Operand b is specified as follows in the assembled object code Bit Tested b 0 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 M CYCLES 3 T STATES...

Page 190: ...444H and bit 4 in the memory location 444H contains 1 after the execution of the Z flag in the F register will contain 0 and bit 4 in memory location 44448 will still contain 1 Bit in memory location...

Page 191: ...ll contain the complement of the indicated bit within the contents of the memory locati pointed to by the sum of the contents register pair I Index Register IX and the two s complement displacement in...

Page 192: ...P V N C If the contents of Index Register IX are 2000H and bit 6 in memory location 2004H contains 1 after the execution of the Z flag in the F register will contain 0 and bit 6 in memory location 20...

Page 193: ...nt of the indicated bit within the contents of the memory location pointed to by the sum of the contents of register pair IY Index Register IY and the two s complement displacement integer d Operand b...

Page 194: ...H P V N C If the contents of Index Register are 2000H and bit 6 in memory location 2004H contains 1 after the execution of the Z flag in the F register sill contain 0 and bit 6 in memory location 200...

Page 195: ...B C D E H L or A is set Operands band r are specified as follows in the assembled object code Bit b Register r a 000 B 000 1 001 C 001 2 010 D 010 3 all E all 4 100 H 100 5 101 L 101 6 110 A 111 7 111...

Page 196: ...r pair HL is set Operand b is specified as follows in the assembled object code Bit Tested b 0 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 If the contents of the HL register pair are 3000H after the...

Page 197: ...gh 0 in the memory location addressed by the sum of the contents of the IX register pair Index Register IX and the two s complement integer d is set Operand b is specified as follows in the assembled...

Page 198: ...If the contents of Index Register are 2000H after the execution of bit 0 in memory location 2003H will be 1 Bit 0 in memory location 2003H is the least significant bit...

Page 199: ...on addressed by the sum of the contents of the IY register pair Index Register IY and the two s complement displacement d is set Operand b is specified as follows in the assembled object code Bit Test...

Page 200: ...If the contents of Index Register IY are 2000H after the execution of bit 0 in memory location 2003H will be 1 Bit 0 in memory location 2003H is the least significant bit...

Page 201: ...of r 1iL IX d or IY d as defined for the analogous SET instructions These various possible opcode operand combinations are assembled as follows in the object code 1 1 1 0 11 0 b7 r 1 1 0 0 11 0 7 b 1...

Page 202: ...2 010 D 010 3 all E all 4 100 H 100 5 101 L 101 6 110 A 111 7 111 RES r RES HL RES IX d RES IY d 8 4 4 15 4 4 4 3 23 4 4 3 5 4 3 23 4 4 3 5 4 3 2 00 3 75 5 75 5 75 bit 6 in register D will be reset Bi...

Page 203: ......

Page 204: ......

Page 205: ...Note The first operand in this assembled object code is the low order byte of a 2 byte address Operand nn is loaded into register pair PC Program Counter and points to the address of the next program...

Page 206: ...rogram Counter is incremented as usual and the program continues with the next sequential instruction Condition cc is programmed as one of eight status which corresponds to condition bits in the Flag...

Page 207: ...C flag in the F register is set and the contents of address 1520 are 03H after the execution of the Program Counter will contain 1520ll and on the next machine cycle the CPU will fetch from address 1...

Page 208: ...ontents of the PC This jump is measured from the address of the instruction opcode and has a range of 126 to 129 bytes The assembler calculate s the displacement e and automatically adjusts for the tw...

Page 209: ...ext instruction is fetched from the location designated by the new contents of the PC The jump is measured from the address of the instruction opcode and has a range of 126 to 129 bytes The assembler...

Page 210: ...The resulting object code and final PC value is shown below 47C LABEL 47D 47E 47F 480 JR C L ABEL 481 38 FA 2 5 complement 6...

Page 211: ...xt instruction is fetched from the location designated by the new contents of the PC The jump is measured from the address of the instruction opcode and has a range of 126 to 129 bytes The assembler c...

Page 212: ...The resulting object code and PC after the jump are shown below 480 LABEL JR NC LABEL 30 PC after jump 481 00...

Page 213: ...is fetched from the location designated by the new contents of the PC The jump is measured from the address of the instruction opcode and has a range of 126 to 129 bytes The assembler calculates the d...

Page 214: ...The resulting object code and final PC value is shown below 300 JR Z LPBEL 301 302 303 304 305 LABEL...

Page 215: ...xt instruction is fetched from the location designated by the new contents of the PC The jump is measured from the address of the instruction opcode and has a range of 126 to 129 bytes The assembler c...

Page 216: ...The resulting object code and final PC value is shown below 47C LABEL 47D 47E 47F 480 JR NZ LABEL 481...

Page 217: ...h the contents of the HL register pair The next instruction is fetched from the location designated by the new contents of the PC If the contents of the Program Counter are 1000ll and the contents of...

Page 218: ...aded with the contents of the IX Register Pair Index Register IX The next instruction is fetched from the location designated by the new contents of the PC If the contents of the Program Counter are l...

Page 219: ...with the contents of the IY register pair Index Register IY The next instruction is fetched from the location designated by the new contents of the PC If the contents of the Program Counter are lOOOH...

Page 220: ...e address of the instruction opcode and has a range of 126 to 129 bytes The assembler calculates the displacement e and automatically adjusts for the twice incremented PC If the result of decrementing...

Page 221: ...ver occurs first LD B 80 Se t up counter LD HL Inbuf Set up pointers LD DE Outbuf OP LD A HL Get next byte from input buffer LD DE A Store in output buffer CP DOH Is it a CR JR Z DONE Yes finished INC...

Page 222: ......

Page 223: ...o be fetched At the end of the subroutine a RETurn instruction can be used to return to the origina program flow by popping the top of the stack back into PC The push is accomplished by first decremen...

Page 224: ...byte instruction CD352lH will be fetched to the CPU for execution The mnemonic equivalent of this is After the execution of this instruction the contents of memory address 300lH will be IAH the conte...

Page 225: ...he end of the subroutine a RETurn instruction can be used to return to the original program flow by popping the top of the stack back into PC If condition cc is false the Program Counter is incremente...

Page 226: ...111 HZ non zero Z zero HC non carry C carry PO parity odd PE parity even P sign positive H sign negative Relevan t Flag Z Z C C p v p v S S If the C Flag in the F register is reset the contents of th...

Page 227: ...emory address 300lH will be lAH the contents of address 3000H will be 4AH the contents of the Stack Pointer will be 3000H and the contents of the Program Counter will be 2l35H pointing to the address...

Page 228: ...the contents of the memory address now pointed to by the SP The SP is now incremented a second time On the following machine cycle the CPU will fetch the next program opcode from the location in memo...

Page 229: ...P is now incremented a second time On the following machine cycle the CPU will fetch the next program opcode from the location in memory now pointed to by the PC If condition cc is false the PC is sim...

Page 230: ...Pointer are ZOOOH the contents of mecory location ZOOOH are B5H and the contents of memory location ZOOIH are IBH then after the execution of the contents of the Stack Pointer will be ZOOZH and the c...

Page 231: ...an I O device that the interrupt routine has been conpleted The REII instruction facilitates the nesting of interrupts allowing higher priority devices to suspend service of lower priority service ro...

Page 232: ...A generates an i terrupt suspending service of B The lEO of A goes low indicating that a higher priority device is being serviced The A routine is completed and a RETl is issu d resetting the lEO of...

Page 233: ...mory location now pointed to by SP and SP is incremented again Control is now returned to the original program flow on the following machine cycle the CPU will fetch the next opcode from the location...

Page 234: ...rvice routine uhich ends with RETN instruction Upon the execution of RETN the former Program Counter contents are popped off the external memory stack low order first resulting in a Stack Pointer cont...

Page 235: ...memory address now pointed to by SP decrementing SP again and loading the low order byte of PC into the address now pointed to by SP The ReSTart instruction allows for a jump to one of eight addresse...

Page 236: ...If the contents of the Program Counter are l5B3R after the execution of the PC will contain DDl8R as the address of the next opcode to be fetched...

Page 237: ......

Page 238: ......

Page 239: ...of the Accumulator also appear on the top half A8 through A15 of the address bus at this time Then one byte from the selected port is placed on the data bus and written into the Accumulator register...

Page 240: ...alf A8 through A15 of the address bus at this time Then one byte from the selected port is placed on the data bus and vritten into register r in the CPU Register r identifies any of the CPU registers...

Page 241: ...reset otherwise Reset Set if parity is even reset otherwise Re se t Not affected R P V If the contents of register Care 07R the contents of register B are lOR and the byte 7BR is available at the peri...

Page 242: ...aced on the data bus and written to the CPU The contents of the HL register pair are then placed on the address bus and the input byte is written into the corresponding location of memory Finally the...

Page 243: ...memory location lOOOH will contain 7BH the HL register pair will contain lOOlH and register B will contain OFH...

Page 244: ...and written to the CPU The contents of the HL register pair are placed on the address bus and the input byte is written into the corresponding location of cemory Then register pair HL is incremented t...

Page 245: ...re 03H the contents of the HL register pair are lOOOH and the following sequence of bytes are available at the peripheral device mapped to I O port of address 07H SlH A9H 03H the HL register pair will...

Page 246: ...e from the selected port is placed on the data bus and written to the CPU The contents of the HL register pair are placed on the address bus and the input byte is written into the corresponding locati...

Page 247: ...peripheral device mapped to I O port address 07H then after the execution of memory location lOOOH will contain 7BH the ilL register pair will contain OFFFH and register B will contain OFH...

Page 248: ...a bus and written to the CPU The contents of the ilL register pair are placed on the address bus and the input byte is written into the corresponding location of memory Then ilL and the byte counter a...

Page 249: ...Bare 03H the contents of the HL register pair are 1000H and the following sequence of bytes are available at the peripheral device apped to I O port address 07H SIll A9H 03H the HL register pair will...

Page 250: ...AccuQulator register A also appear on the top half AB through A15 of the address bus at this tiJ le Then the byte contained in the Accumulator is placed on the data bus and written into the selected p...

Page 251: ...e placed on the top half A8 through A15 of the address bus at this time Then the byte contained in register r is placed on the data bus and written into the selected peripheral device Register r ident...

Page 252: ...If the contents of register Care 01ll and the contents of register Dare SAH after the execution of the byte SAH will have been written to the peripheral device mapped to I O ort address 01H...

Page 253: ...he I O device at one of 256 possible ports Register B may be used as a byte counter and its decremented value is placed on the top half A8 through A15 of the address bus The byte to be output is place...

Page 254: ...register B will contain OFH the HL register pair will contain 1001H and the byte 59H will have been written to the peripheral device mapped to I O port address 07H...

Page 255: ...e counter and its decremented value is placed on the top half A8 through A15 of the address bus at this time Next the byte to be output is placed on the data bus and written into the selected peripher...

Page 256: ...he contents of the HL register pair are 1000H and memory locations have the following contents l OOOH 100lH 1002H 5lH A9H 03H the HL register pair will contain 1003H register B will contain zero and a...

Page 257: ...C are placed on the bottom half AD through A7 of the address bus to select the I O device at one of 256 possible ports Register B may be used as a byte counter and its decremented value is placed on t...

Page 258: ...air are 1000H and the contents of memory location 1000H are 59H after the execution of register B will contain OFH the HL register pair will contain OFFFH and the byte 59H will have been written to th...

Page 259: ...ter and its decremented value is placed on the top half A8 through A15 of the address bus at this time Next the byte to be output is placed on the data bus and written into the selected peripheral dev...

Page 260: ...the contents of the RL register pair are lOOOH and memory locations have the following contents OFFER OFFFH lOOOH 5lR A9H 03H the HL register pair will contain OFFDR register B will contain zero and...

Page 261: ......

Page 262: ......

Page 263: ...thmetic The carry bit is set or reset depending on the operation being performed For ADD instructions that generate a carry and SUBTRACT instructions that generate a borrow the Carry Flag will be set...

Page 264: ...in the Accumulator is greater than the maximum possible number 127 or is less than the minimum possible number 128 This overflow condition can be determined by examining the sign bits of the operands...

Page 265: ...LDDR the P V flag monitors the state of the byte count register BC When decrementing the byte counter results in a zero value the flag is reset to 0 otherwise the flag is a Logic 1 During LD A I and...

Page 266: ...and OUTD if the result of B 1 is zero the Z flag is set otherwise it is reset Also for byte inputs from I O devices using IN r C the Z Flag is set to indicate a zero byte input The 5ign Flag 5 stores...

Page 267: ......

Page 268: ...t BIT b of Reg r Call subroutine at location nn if condition cc 1s true Unconditional call subroutine at location nn Complement carry flag Compare operand 8 with Ace Cocpare location lIL and Ace decre...

Page 269: ...Increment location IY d 107 Increment Reg r 102 In c rem e n t Re g p air s s 138 Load location HL with input from port C decrement HL and B 5 Load location HL with input from port C decrement HL and...

Page 270: ...h value n 19 2 1 10 LD IX d r Load location IX d with Reg r 14 2 1 7 LD IY nn Load IY with value nn 34 2 2 3 LD IY nn Load IY with location nn 39 2 2 7 LD I Y d n Load location IY d with value n 20 2...

Page 271: ...B 252 Load IX with top of staCk Load IY with top of stack 54 Load Reg pair qq with top of stack 51 Load IX onto stack 49 Load IY onto stack 50 Load Reg pair qq onto stack 48 Reset Bit b of operand m 2...

Page 272: ...hift operand m right logical 177 Subtract operand s from Ace 90 Exclusive OR operand 8 and Ace 98 2 7 16 2 10 7 2 6 3 2 5 5 2 8 6 2 8 7 2 8 8 2 8 5 2 7 12 2 7 13 2 7 14 2 4 7 2 4 11 Information furnis...

Page 273: ...Hannover 1 Lange Laube 19 Tel 0511 17522 3 Telex 0923195 8000 Miinchen 40 Gernotstrasse 10 Tel 089 304270 304485 Telex 05215784 8500 Nurnberg 15 Parsifalstrasse 10 Tel 0911 40645 7000 Stuttgart 80 Kal...

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